1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 CompuLab, Ltd. 4 * Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Based on omap3_beagle.h 8 * (C) Copyright 2006-2008 9 * Texas Instruments. 10 * Richard Woodruff <r-woodruff2@ti.com> 11 * Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_SYS_CACHELINE_SIZE 64 20 21 /* 22 * High Level Configuration Options 23 */ 24 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/omap.h> 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_MISC_INIT_R 34 35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 37 #define CONFIG_INITRD_TAG 38 #define CONFIG_REVISION_TAG 39 #define CONFIG_SERIAL_TAG 40 41 /* 42 * Size of malloc() pool 43 */ 44 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 45 /* Sector */ 46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 47 48 /* 49 * Hardware drivers 50 */ 51 52 /* 53 * NS16550 Configuration 54 */ 55 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56 57 #define CONFIG_SYS_NS16550_SERIAL 58 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 59 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 60 61 /* 62 * select serial console configuration 63 */ 64 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 65 #define CONFIG_SERIAL3 3 /* UART3 */ 66 67 /* allow to overwrite serial and ethaddr */ 68 #define CONFIG_ENV_OVERWRITE 69 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 70 115200} 71 72 /* USB device configuration */ 73 #define CONFIG_USB_DEVICE 74 #define CONFIG_USB_TTY 75 76 /* commands to include */ 77 78 #define CONFIG_SYS_I2C 79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 81 #define CONFIG_SYS_I2C_EEPROM_BUS 0 82 #define CONFIG_I2C_MULTI_BUS 83 84 /* 85 * TWL4030 86 */ 87 #define CONFIG_TWL4030_LED 88 89 /* 90 * Board NAND Info. 91 */ 92 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 93 /* to access nand at */ 94 /* CS0 */ 95 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 96 /* devices */ 97 98 /* Environment information */ 99 #define CONFIG_EXTRA_ENV_SETTINGS \ 100 "loadaddr=0x82000000\0" \ 101 "usbtty=cdc_acm\0" \ 102 "console=ttyO2,115200n8\0" \ 103 "mpurate=500\0" \ 104 "vram=12M\0" \ 105 "dvimode=1024x768MR-16@60\0" \ 106 "defaultdisplay=dvi\0" \ 107 "mmcdev=0\0" \ 108 "mmcroot=/dev/mmcblk0p2 rw\0" \ 109 "mmcrootfstype=ext4 rootwait\0" \ 110 "nandroot=/dev/mtdblock4 rw\0" \ 111 "nandrootfstype=ubifs\0" \ 112 "mmcargs=setenv bootargs console=${console} " \ 113 "mpurate=${mpurate} " \ 114 "vram=${vram} " \ 115 "omapfb.mode=dvi:${dvimode} " \ 116 "omapdss.def_disp=${defaultdisplay} " \ 117 "root=${mmcroot} " \ 118 "rootfstype=${mmcrootfstype}\0" \ 119 "nandargs=setenv bootargs console=${console} " \ 120 "mpurate=${mpurate} " \ 121 "vram=${vram} " \ 122 "omapfb.mode=dvi:${dvimode} " \ 123 "omapdss.def_disp=${defaultdisplay} " \ 124 "root=${nandroot} " \ 125 "rootfstype=${nandrootfstype}\0" \ 126 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 127 "bootscript=echo Running bootscript from mmc ...; " \ 128 "source ${loadaddr}\0" \ 129 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 130 "mmcboot=echo Booting from mmc ...; " \ 131 "run mmcargs; " \ 132 "bootm ${loadaddr}\0" \ 133 "nandboot=echo Booting from nand ...; " \ 134 "run nandargs; " \ 135 "nand read ${loadaddr} 2a0000 400000; " \ 136 "bootm ${loadaddr}\0" \ 137 138 #define CONFIG_BOOTCOMMAND \ 139 "mmc dev ${mmcdev}; if mmc rescan; then " \ 140 "if run loadbootscript; then " \ 141 "run bootscript; " \ 142 "else " \ 143 "if run loaduimage; then " \ 144 "run mmcboot; " \ 145 "else run nandboot; " \ 146 "fi; " \ 147 "fi; " \ 148 "else run nandboot; fi" 149 150 /* 151 * Miscellaneous configurable options 152 */ 153 #define CONFIG_TIMESTAMP 154 #define CONFIG_SYS_AUTOLOAD "no" 155 156 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 157 /* works on */ 158 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 159 0x01F00000) /* 31MB */ 160 161 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 162 /* load address */ 163 164 /* 165 * OMAP3 has 12 GP timers, they can be driven by the system clock 166 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 167 * This rate is divided by a local divisor. 168 */ 169 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 170 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 171 172 /*----------------------------------------------------------------------- 173 * Physical Memory Map 174 */ 175 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 176 177 /*----------------------------------------------------------------------- 178 * FLASH and environment organization 179 */ 180 181 /* **** PISMO SUPPORT *** */ 182 /* Monitor at start of flash */ 183 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 184 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 185 186 #define CONFIG_ENV_OFFSET 0x260000 187 #define CONFIG_ENV_ADDR 0x260000 188 189 /* additions for new relocation code, must be added to all boards */ 190 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 191 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 192 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 193 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 194 CONFIG_SYS_INIT_RAM_SIZE - \ 195 GENERATED_GBL_DATA_SIZE) 196 197 /* Status LED */ 198 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 199 200 #define CONFIG_SPLASHIMAGE_GUARD 201 202 /* Display Configuration */ 203 #define CONFIG_VIDEO_OMAP3 204 #define LCD_BPP LCD_COLOR16 205 206 #define CONFIG_SPLASH_SCREEN 207 #define CONFIG_SPLASH_SOURCE 208 #define CONFIG_BMP_16BPP 209 #define CONFIG_SCF0403_LCD 210 211 /* Defines for SPL */ 212 213 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 214 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 215 216 #define CONFIG_SPL_NAND_BASE 217 #define CONFIG_SPL_NAND_DRIVERS 218 #define CONFIG_SPL_NAND_ECC 219 220 /* NAND boot config */ 221 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 222 #define CONFIG_SYS_NAND_PAGE_COUNT 64 223 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 224 #define CONFIG_SYS_NAND_OOBSIZE 64 225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 227 /* 228 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 229 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 230 */ 231 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 232 10, 11, 12 } 233 #define CONFIG_SYS_NAND_ECCSIZE 512 234 #define CONFIG_SYS_NAND_ECCBYTES 3 235 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 236 237 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 238 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 239 240 #define CONFIG_SPL_TEXT_BASE 0x40200800 241 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 242 CONFIG_SPL_TEXT_BASE) 243 244 /* 245 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 246 * older x-loader implementations. And move the BSS area so that it 247 * doesn't overlap with TEXT_BASE. 248 */ 249 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 250 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 251 252 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 253 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 254 255 /* EEPROM */ 256 #define CONFIG_ENV_EEPROM_IS_ON_I2C 257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 260 #define CONFIG_SYS_EEPROM_SIZE 256 261 262 #endif /* __CONFIG_H */ 263