1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 27 #include <asm/arch/cpu.h> /* get chip and board defs */ 28 #include <asm/arch/omap.h> 29 30 /* Clock Defines */ 31 #define V_OSCK 26000000 /* Clock output from T2 */ 32 #define V_SCLK (V_OSCK >> 1) 33 34 #define CONFIG_MISC_INIT_R 35 36 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 37 #define CONFIG_SETUP_MEMORY_TAGS 38 #define CONFIG_INITRD_TAG 39 #define CONFIG_REVISION_TAG 40 #define CONFIG_SERIAL_TAG 41 42 /* 43 * Size of malloc() pool 44 */ 45 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 46 /* Sector */ 47 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 48 49 /* 50 * Hardware drivers 51 */ 52 53 /* 54 * NS16550 Configuration 55 */ 56 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 #define CONFIG_SYS_NS16550_SERIAL 59 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 60 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 61 62 /* 63 * select serial console configuration 64 */ 65 #define CONFIG_CONS_INDEX 3 66 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 67 #define CONFIG_SERIAL3 3 /* UART3 */ 68 69 /* allow to overwrite serial and ethaddr */ 70 #define CONFIG_ENV_OVERWRITE 71 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 72 115200} 73 74 /* USB device configuration */ 75 #define CONFIG_USB_DEVICE 76 #define CONFIG_USB_TTY 77 78 /* commands to include */ 79 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 80 #define CONFIG_MTD_PARTITIONS 81 82 #define CONFIG_SYS_I2C 83 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 84 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 85 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 86 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 87 #define CONFIG_SYS_I2C_EEPROM_BUS 0 88 #define CONFIG_I2C_MULTI_BUS 89 90 /* 91 * TWL4030 92 */ 93 #define CONFIG_TWL4030_LED 94 95 /* 96 * Board NAND Info. 97 */ 98 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 99 /* to access nand */ 100 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 101 /* to access nand at */ 102 /* CS0 */ 103 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 104 /* devices */ 105 106 /* Environment information */ 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "loadaddr=0x82000000\0" \ 109 "usbtty=cdc_acm\0" \ 110 "console=ttyO2,115200n8\0" \ 111 "mpurate=500\0" \ 112 "vram=12M\0" \ 113 "dvimode=1024x768MR-16@60\0" \ 114 "defaultdisplay=dvi\0" \ 115 "mmcdev=0\0" \ 116 "mmcroot=/dev/mmcblk0p2 rw\0" \ 117 "mmcrootfstype=ext4 rootwait\0" \ 118 "nandroot=/dev/mtdblock4 rw\0" \ 119 "nandrootfstype=ubifs\0" \ 120 "mmcargs=setenv bootargs console=${console} " \ 121 "mpurate=${mpurate} " \ 122 "vram=${vram} " \ 123 "omapfb.mode=dvi:${dvimode} " \ 124 "omapdss.def_disp=${defaultdisplay} " \ 125 "root=${mmcroot} " \ 126 "rootfstype=${mmcrootfstype}\0" \ 127 "nandargs=setenv bootargs console=${console} " \ 128 "mpurate=${mpurate} " \ 129 "vram=${vram} " \ 130 "omapfb.mode=dvi:${dvimode} " \ 131 "omapdss.def_disp=${defaultdisplay} " \ 132 "root=${nandroot} " \ 133 "rootfstype=${nandrootfstype}\0" \ 134 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 135 "bootscript=echo Running bootscript from mmc ...; " \ 136 "source ${loadaddr}\0" \ 137 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 138 "mmcboot=echo Booting from mmc ...; " \ 139 "run mmcargs; " \ 140 "bootm ${loadaddr}\0" \ 141 "nandboot=echo Booting from nand ...; " \ 142 "run nandargs; " \ 143 "nand read ${loadaddr} 2a0000 400000; " \ 144 "bootm ${loadaddr}\0" \ 145 146 #define CONFIG_BOOTCOMMAND \ 147 "mmc dev ${mmcdev}; if mmc rescan; then " \ 148 "if run loadbootscript; then " \ 149 "run bootscript; " \ 150 "else " \ 151 "if run loaduimage; then " \ 152 "run mmcboot; " \ 153 "else run nandboot; " \ 154 "fi; " \ 155 "fi; " \ 156 "else run nandboot; fi" 157 158 /* 159 * Miscellaneous configurable options 160 */ 161 #define CONFIG_AUTO_COMPLETE 162 #define CONFIG_CMDLINE_EDITING 163 #define CONFIG_TIMESTAMP 164 #define CONFIG_SYS_AUTOLOAD "no" 165 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 166 167 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 168 /* works on */ 169 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 170 0x01F00000) /* 31MB */ 171 172 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 173 /* load address */ 174 175 /* 176 * OMAP3 has 12 GP timers, they can be driven by the system clock 177 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 178 * This rate is divided by a local divisor. 179 */ 180 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 181 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 182 183 /*----------------------------------------------------------------------- 184 * Physical Memory Map 185 */ 186 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 187 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 188 189 /*----------------------------------------------------------------------- 190 * FLASH and environment organization 191 */ 192 193 /* **** PISMO SUPPORT *** */ 194 /* Monitor at start of flash */ 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 196 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 197 198 #define CONFIG_ENV_OFFSET 0x260000 199 #define CONFIG_ENV_ADDR 0x260000 200 201 /* additions for new relocation code, must be added to all boards */ 202 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 203 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 204 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 205 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 206 CONFIG_SYS_INIT_RAM_SIZE - \ 207 GENERATED_GBL_DATA_SIZE) 208 209 /* Status LED */ 210 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 211 212 #define CONFIG_SPLASHIMAGE_GUARD 213 214 /* Display Configuration */ 215 #define CONFIG_VIDEO_OMAP3 216 #define LCD_BPP LCD_COLOR16 217 218 #define CONFIG_SPLASH_SCREEN 219 #define CONFIG_SPLASH_SOURCE 220 #define CONFIG_BMP_16BPP 221 #define CONFIG_SCF0403_LCD 222 223 /* Defines for SPL */ 224 #define CONFIG_SPL_FRAMEWORK 225 226 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 227 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 228 229 #define CONFIG_SPL_NAND_BASE 230 #define CONFIG_SPL_NAND_DRIVERS 231 #define CONFIG_SPL_NAND_ECC 232 233 /* NAND boot config */ 234 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 235 #define CONFIG_SYS_NAND_PAGE_COUNT 64 236 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 237 #define CONFIG_SYS_NAND_OOBSIZE 64 238 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 239 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 240 /* 241 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 242 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 243 */ 244 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 245 10, 11, 12 } 246 #define CONFIG_SYS_NAND_ECCSIZE 512 247 #define CONFIG_SYS_NAND_ECCBYTES 3 248 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 249 250 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 251 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 252 253 #define CONFIG_SPL_TEXT_BASE 0x40200800 254 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 255 CONFIG_SPL_TEXT_BASE) 256 257 /* 258 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 259 * older x-loader implementations. And move the BSS area so that it 260 * doesn't overlap with TEXT_BASE. 261 */ 262 #define CONFIG_SYS_TEXT_BASE 0x80008000 263 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 264 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 265 266 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 267 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 268 269 /* EEPROM */ 270 #define CONFIG_ENV_EEPROM_IS_ON_I2C 271 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 272 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 273 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 274 #define CONFIG_SYS_EEPROM_SIZE 256 275 276 #endif /* __CONFIG_H */ 277