1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 #define CONFIG_OMAP_COMMON 29 /* Common ARM Erratas */ 30 #define CONFIG_ARM_ERRATA_454179 31 #define CONFIG_ARM_ERRATA_430973 32 #define CONFIG_ARM_ERRATA_621766 33 34 #define CONFIG_SDRC /* The chip has SDRC controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap.h> 38 39 /* Clock Defines */ 40 #define V_OSCK 26000000 /* Clock output from T2 */ 41 #define V_SCLK (V_OSCK >> 1) 42 43 #define CONFIG_MISC_INIT_R 44 45 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 46 #define CONFIG_SETUP_MEMORY_TAGS 47 #define CONFIG_INITRD_TAG 48 #define CONFIG_REVISION_TAG 49 #define CONFIG_SERIAL_TAG 50 51 /* 52 * Size of malloc() pool 53 */ 54 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 55 /* Sector */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 57 58 /* 59 * Hardware drivers 60 */ 61 62 /* 63 * NS16550 Configuration 64 */ 65 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 66 67 #define CONFIG_SYS_NS16550_SERIAL 68 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 69 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 70 71 /* 72 * select serial console configuration 73 */ 74 #define CONFIG_CONS_INDEX 3 75 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 76 #define CONFIG_SERIAL3 3 /* UART3 */ 77 78 /* allow to overwrite serial and ethaddr */ 79 #define CONFIG_ENV_OVERWRITE 80 #define CONFIG_BAUDRATE 115200 81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 82 115200} 83 84 #define CONFIG_GENERIC_MMC 85 #define CONFIG_MMC 86 #define CONFIG_OMAP_HSMMC 87 #define CONFIG_DOS_PARTITION 88 89 /* USB */ 90 #define CONFIG_USB_OMAP3 91 #define CONFIG_USB_EHCI 92 #define CONFIG_USB_EHCI_OMAP 93 #define CONFIG_USB_MUSB_UDC 94 #define CONFIG_TWL4030_USB 95 96 /* USB device configuration */ 97 #define CONFIG_USB_DEVICE 98 #define CONFIG_USB_TTY 99 100 /* commands to include */ 101 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 102 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 103 #define CONFIG_MTD_PARTITIONS 104 #define MTDIDS_DEFAULT "nand0=nand" 105 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 106 "1920k(u-boot),256k(u-boot-env),"\ 107 "4m(kernel),-(fs)" 108 109 #define CONFIG_CMD_NAND /* NAND support */ 110 111 #define CONFIG_SYS_NO_FLASH 112 #define CONFIG_SYS_I2C 113 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 114 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 115 #define CONFIG_SYS_I2C_OMAP34XX 116 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 118 #define CONFIG_SYS_I2C_EEPROM_BUS 0 119 #define CONFIG_I2C_MULTI_BUS 120 121 /* 122 * TWL4030 123 */ 124 #define CONFIG_TWL4030_POWER 125 #define CONFIG_TWL4030_LED 126 127 /* 128 * Board NAND Info. 129 */ 130 #define CONFIG_NAND_OMAP_GPMC 131 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 132 /* to access nand */ 133 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 134 /* to access nand at */ 135 /* CS0 */ 136 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 137 /* devices */ 138 139 /* Environment information */ 140 #define CONFIG_EXTRA_ENV_SETTINGS \ 141 "loadaddr=0x82000000\0" \ 142 "usbtty=cdc_acm\0" \ 143 "console=ttyO2,115200n8\0" \ 144 "mpurate=500\0" \ 145 "vram=12M\0" \ 146 "dvimode=1024x768MR-16@60\0" \ 147 "defaultdisplay=dvi\0" \ 148 "mmcdev=0\0" \ 149 "mmcroot=/dev/mmcblk0p2 rw\0" \ 150 "mmcrootfstype=ext4 rootwait\0" \ 151 "nandroot=/dev/mtdblock4 rw\0" \ 152 "nandrootfstype=ubifs\0" \ 153 "mmcargs=setenv bootargs console=${console} " \ 154 "mpurate=${mpurate} " \ 155 "vram=${vram} " \ 156 "omapfb.mode=dvi:${dvimode} " \ 157 "omapdss.def_disp=${defaultdisplay} " \ 158 "root=${mmcroot} " \ 159 "rootfstype=${mmcrootfstype}\0" \ 160 "nandargs=setenv bootargs console=${console} " \ 161 "mpurate=${mpurate} " \ 162 "vram=${vram} " \ 163 "omapfb.mode=dvi:${dvimode} " \ 164 "omapdss.def_disp=${defaultdisplay} " \ 165 "root=${nandroot} " \ 166 "rootfstype=${nandrootfstype}\0" \ 167 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 168 "bootscript=echo Running bootscript from mmc ...; " \ 169 "source ${loadaddr}\0" \ 170 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 171 "mmcboot=echo Booting from mmc ...; " \ 172 "run mmcargs; " \ 173 "bootm ${loadaddr}\0" \ 174 "nandboot=echo Booting from nand ...; " \ 175 "run nandargs; " \ 176 "nand read ${loadaddr} 2a0000 400000; " \ 177 "bootm ${loadaddr}\0" \ 178 179 #define CONFIG_BOOTCOMMAND \ 180 "mmc dev ${mmcdev}; if mmc rescan; then " \ 181 "if run loadbootscript; then " \ 182 "run bootscript; " \ 183 "else " \ 184 "if run loaduimage; then " \ 185 "run mmcboot; " \ 186 "else run nandboot; " \ 187 "fi; " \ 188 "fi; " \ 189 "else run nandboot; fi" 190 191 /* 192 * Miscellaneous configurable options 193 */ 194 #define CONFIG_AUTO_COMPLETE 195 #define CONFIG_CMDLINE_EDITING 196 #define CONFIG_TIMESTAMP 197 #define CONFIG_SYS_AUTOLOAD "no" 198 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 199 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 200 /* Print Buffer Size */ 201 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 202 sizeof(CONFIG_SYS_PROMPT) + 16) 203 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 204 /* Boot Argument Buffer Size */ 205 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 206 207 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 208 /* works on */ 209 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 210 0x01F00000) /* 31MB */ 211 212 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 213 /* load address */ 214 215 /* 216 * OMAP3 has 12 GP timers, they can be driven by the system clock 217 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 218 * This rate is divided by a local divisor. 219 */ 220 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 221 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 222 223 /*----------------------------------------------------------------------- 224 * Physical Memory Map 225 */ 226 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 227 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 228 229 /*----------------------------------------------------------------------- 230 * FLASH and environment organization 231 */ 232 233 /* **** PISMO SUPPORT *** */ 234 /* Monitor at start of flash */ 235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 236 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 237 238 #define CONFIG_ENV_IS_IN_NAND 239 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 240 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 241 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 242 243 #if defined(CONFIG_CMD_NET) 244 #define CONFIG_SMC911X 245 #define CONFIG_SMC911X_32_BIT 246 #define CM_T3X_SMC911X_BASE 0x2C000000 247 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 248 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 249 #endif /* (CONFIG_CMD_NET) */ 250 251 /* additions for new relocation code, must be added to all boards */ 252 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 254 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 255 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 256 CONFIG_SYS_INIT_RAM_SIZE - \ 257 GENERATED_GBL_DATA_SIZE) 258 259 /* Status LED */ 260 #define CONFIG_STATUS_LED /* Status LED enabled */ 261 #define CONFIG_BOARD_SPECIFIC_LED 262 #define CONFIG_GPIO_LED 263 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 264 #define GREEN_LED_DEV 0 265 #define STATUS_LED_BIT GREEN_LED_GPIO 266 #define STATUS_LED_STATE STATUS_LED_ON 267 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 268 #define STATUS_LED_BOOT GREEN_LED_DEV 269 270 #define CONFIG_SPLASHIMAGE_GUARD 271 272 /* GPIO banks */ 273 #ifdef CONFIG_STATUS_LED 274 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 275 #endif 276 277 /* Display Configuration */ 278 #define CONFIG_OMAP3_GPIO_2 279 #define CONFIG_OMAP3_GPIO_5 280 #define CONFIG_VIDEO_OMAP3 281 #define LCD_BPP LCD_COLOR16 282 283 #define CONFIG_SPLASH_SCREEN 284 #define CONFIG_SPLASH_SOURCE 285 #define CONFIG_CMD_BMP 286 #define CONFIG_BMP_16BPP 287 #define CONFIG_SCF0403_LCD 288 289 #define CONFIG_OMAP3_SPI 290 291 /* Defines for SPL */ 292 #define CONFIG_SPL_FRAMEWORK 293 #define CONFIG_SPL_NAND_SIMPLE 294 295 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 296 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 297 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 298 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 299 300 #define CONFIG_SPL_BOARD_INIT 301 #define CONFIG_SPL_NAND_BASE 302 #define CONFIG_SPL_NAND_DRIVERS 303 #define CONFIG_SPL_NAND_ECC 304 #define CONFIG_SPL_OMAP3_ID_NAND 305 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 306 307 /* NAND boot config */ 308 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 309 #define CONFIG_SYS_NAND_PAGE_COUNT 64 310 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 311 #define CONFIG_SYS_NAND_OOBSIZE 64 312 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 313 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 314 /* 315 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 316 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 317 */ 318 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 319 10, 11, 12 } 320 #define CONFIG_SYS_NAND_ECCSIZE 512 321 #define CONFIG_SYS_NAND_ECCBYTES 3 322 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 323 324 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 325 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 326 327 #define CONFIG_SPL_TEXT_BASE 0x40200800 328 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 329 CONFIG_SPL_TEXT_BASE) 330 331 /* 332 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 333 * older x-loader implementations. And move the BSS area so that it 334 * doesn't overlap with TEXT_BASE. 335 */ 336 #define CONFIG_SYS_TEXT_BASE 0x80008000 337 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 338 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 339 340 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 341 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 342 343 /* EEPROM */ 344 #define CONFIG_CMD_EEPROM 345 #define CONFIG_ENV_EEPROM_IS_ON_I2C 346 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 347 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 348 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 349 #define CONFIG_SYS_EEPROM_SIZE 256 350 351 #define CONFIG_CMD_EEPROM_LAYOUT 352 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 353 354 #endif /* __CONFIG_H */ 355