1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CMD_GPIO 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 27 #define CONFIG_OMAP_COMMON 28 29 #define CONFIG_SDRC /* The chip has SDRC controller */ 30 31 #include <asm/arch/cpu.h> /* get chip and board defs */ 32 #include <asm/arch/omap3.h> 33 34 /* 35 * Display CPU and Board information 36 */ 37 #define CONFIG_DISPLAY_CPUINFO 38 #define CONFIG_DISPLAY_BOARDINFO 39 40 /* Clock Defines */ 41 #define V_OSCK 26000000 /* Clock output from T2 */ 42 #define V_SCLK (V_OSCK >> 1) 43 44 #define CONFIG_MISC_INIT_R 45 46 #define CONFIG_OF_LIBFDT 1 47 48 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 49 #define CONFIG_SETUP_MEMORY_TAGS 50 #define CONFIG_INITRD_TAG 51 #define CONFIG_REVISION_TAG 52 #define CONFIG_SERIAL_TAG 53 54 /* 55 * Size of malloc() pool 56 */ 57 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 58 /* Sector */ 59 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 60 61 /* 62 * Hardware drivers 63 */ 64 65 /* 66 * NS16550 Configuration 67 */ 68 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69 70 #define CONFIG_SYS_NS16550 71 #define CONFIG_SYS_NS16550_SERIAL 72 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 74 75 /* 76 * select serial console configuration 77 */ 78 #define CONFIG_CONS_INDEX 3 79 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 80 #define CONFIG_SERIAL3 3 /* UART3 */ 81 82 /* allow to overwrite serial and ethaddr */ 83 #define CONFIG_ENV_OVERWRITE 84 #define CONFIG_BAUDRATE 115200 85 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 86 115200} 87 88 #define CONFIG_GENERIC_MMC 89 #define CONFIG_MMC 90 #define CONFIG_OMAP_HSMMC 91 #define CONFIG_DOS_PARTITION 92 93 /* USB */ 94 #define CONFIG_USB_OMAP3 95 #define CONFIG_USB_EHCI 96 #define CONFIG_USB_EHCI_OMAP 97 #define CONFIG_USB_STORAGE 98 #define CONFIG_MUSB_UDC 99 #define CONFIG_TWL4030_USB 100 #define CONFIG_CMD_USB 101 102 /* USB device configuration */ 103 #define CONFIG_USB_DEVICE 104 #define CONFIG_USB_TTY 105 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 106 107 /* commands to include */ 108 #include <config_cmd_default.h> 109 110 #define CONFIG_CMD_CACHE 111 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 112 #define CONFIG_CMD_FAT /* FAT support */ 113 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 114 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 115 #define CONFIG_MTD_PARTITIONS 116 #define MTDIDS_DEFAULT "nand0=nand" 117 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 118 "1920k(u-boot),256k(u-boot-env),"\ 119 "4m(kernel),-(fs)" 120 121 #define CONFIG_CMD_I2C /* I2C serial bus support */ 122 #define CONFIG_CMD_MMC /* MMC support */ 123 #define CONFIG_CMD_NAND /* NAND support */ 124 #define CONFIG_CMD_DHCP 125 #define CONFIG_CMD_PING 126 127 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 128 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 129 #undef CONFIG_CMD_IMLS /* List all found images */ 130 131 #define CONFIG_SYS_NO_FLASH 132 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 134 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 135 #define CONFIG_SYS_I2C_OMAP34XX 136 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 137 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 138 #define CONFIG_SYS_I2C_EEPROM_BUS 0 139 #define CONFIG_I2C_MULTI_BUS 140 141 /* 142 * TWL4030 143 */ 144 #define CONFIG_TWL4030_POWER 145 #define CONFIG_TWL4030_LED 146 147 /* 148 * Board NAND Info. 149 */ 150 #define CONFIG_SYS_NAND_QUIET_TEST 151 #define CONFIG_NAND_OMAP_GPMC 152 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 153 /* to access nand */ 154 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 155 /* to access nand at */ 156 /* CS0 */ 157 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 158 /* devices */ 159 160 /* Environment information */ 161 #define CONFIG_BOOTDELAY 3 162 #define CONFIG_ZERO_BOOTDELAY_CHECK 163 164 #define CONFIG_EXTRA_ENV_SETTINGS \ 165 "loadaddr=0x82000000\0" \ 166 "usbtty=cdc_acm\0" \ 167 "console=ttyO2,115200n8\0" \ 168 "mpurate=500\0" \ 169 "vram=12M\0" \ 170 "dvimode=1024x768MR-16@60\0" \ 171 "defaultdisplay=dvi\0" \ 172 "mmcdev=0\0" \ 173 "mmcroot=/dev/mmcblk0p2 rw\0" \ 174 "mmcrootfstype=ext4 rootwait\0" \ 175 "nandroot=/dev/mtdblock4 rw\0" \ 176 "nandrootfstype=ubifs\0" \ 177 "mmcargs=setenv bootargs console=${console} " \ 178 "mpurate=${mpurate} " \ 179 "vram=${vram} " \ 180 "omapfb.mode=dvi:${dvimode} " \ 181 "omapdss.def_disp=${defaultdisplay} " \ 182 "root=${mmcroot} " \ 183 "rootfstype=${mmcrootfstype}\0" \ 184 "nandargs=setenv bootargs console=${console} " \ 185 "mpurate=${mpurate} " \ 186 "vram=${vram} " \ 187 "omapfb.mode=dvi:${dvimode} " \ 188 "omapdss.def_disp=${defaultdisplay} " \ 189 "root=${nandroot} " \ 190 "rootfstype=${nandrootfstype}\0" \ 191 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 192 "bootscript=echo Running bootscript from mmc ...; " \ 193 "source ${loadaddr}\0" \ 194 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 195 "mmcboot=echo Booting from mmc ...; " \ 196 "run mmcargs; " \ 197 "bootm ${loadaddr}\0" \ 198 "nandboot=echo Booting from nand ...; " \ 199 "run nandargs; " \ 200 "nand read ${loadaddr} 2a0000 400000; " \ 201 "bootm ${loadaddr}\0" \ 202 203 #define CONFIG_CMD_BOOTZ 204 #define CONFIG_BOOTCOMMAND \ 205 "mmc dev ${mmcdev}; if mmc rescan; then " \ 206 "if run loadbootscript; then " \ 207 "run bootscript; " \ 208 "else " \ 209 "if run loaduimage; then " \ 210 "run mmcboot; " \ 211 "else run nandboot; " \ 212 "fi; " \ 213 "fi; " \ 214 "else run nandboot; fi" 215 216 /* 217 * Miscellaneous configurable options 218 */ 219 #define CONFIG_AUTO_COMPLETE 220 #define CONFIG_CMDLINE_EDITING 221 #define CONFIG_TIMESTAMP 222 #define CONFIG_SYS_AUTOLOAD "no" 223 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 224 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 225 #define CONFIG_SYS_PROMPT "CM-T3x # " 226 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 227 /* Print Buffer Size */ 228 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 229 sizeof(CONFIG_SYS_PROMPT) + 16) 230 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 231 /* Boot Argument Buffer Size */ 232 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 233 234 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 235 /* works on */ 236 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 237 0x01F00000) /* 31MB */ 238 239 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 240 /* load address */ 241 242 /* 243 * OMAP3 has 12 GP timers, they can be driven by the system clock 244 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 245 * This rate is divided by a local divisor. 246 */ 247 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 248 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 249 250 /*----------------------------------------------------------------------- 251 * Physical Memory Map 252 */ 253 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 254 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 255 256 /*----------------------------------------------------------------------- 257 * FLASH and environment organization 258 */ 259 260 /* **** PISMO SUPPORT *** */ 261 /* Monitor at start of flash */ 262 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 263 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 264 265 #define CONFIG_ENV_IS_IN_NAND 266 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 267 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 268 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 269 270 #if defined(CONFIG_CMD_NET) 271 #define CONFIG_SMC911X 272 #define CONFIG_SMC911X_32_BIT 273 #define CM_T3X_SMC911X_BASE 0x2C000000 274 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 275 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 276 #endif /* (CONFIG_CMD_NET) */ 277 278 /* additions for new relocation code, must be added to all boards */ 279 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 280 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 281 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 282 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 283 CONFIG_SYS_INIT_RAM_SIZE - \ 284 GENERATED_GBL_DATA_SIZE) 285 286 /* Status LED */ 287 #define CONFIG_STATUS_LED /* Status LED enabled */ 288 #define CONFIG_BOARD_SPECIFIC_LED 289 #define CONFIG_GPIO_LED 290 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 291 #define GREEN_LED_DEV 0 292 #define STATUS_LED_BIT GREEN_LED_GPIO 293 #define STATUS_LED_STATE STATUS_LED_ON 294 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 295 #define STATUS_LED_BOOT GREEN_LED_DEV 296 297 #define CONFIG_SPLASHIMAGE_GUARD 298 299 /* GPIO banks */ 300 #ifdef CONFIG_STATUS_LED 301 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 302 #endif 303 304 /* Display Configuration */ 305 #define CONFIG_OMAP3_GPIO_2 306 #define CONFIG_OMAP3_GPIO_5 307 #define CONFIG_VIDEO_OMAP3 308 #define LCD_BPP LCD_COLOR16 309 310 #define CONFIG_LCD 311 #define CONFIG_SPLASH_SCREEN 312 #define CONFIG_CMD_BMP 313 #define CONFIG_BMP_16BPP 314 #define CONFIG_SCF0403_LCD 315 316 #define CONFIG_OMAP3_SPI 317 318 /* Defines for SPL */ 319 #define CONFIG_SPL_FRAMEWORK 320 #define CONFIG_SPL_NAND_SIMPLE 321 322 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 323 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 324 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 325 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" 326 327 #define CONFIG_SPL_BOARD_INIT 328 #define CONFIG_SPL_LIBCOMMON_SUPPORT 329 #define CONFIG_SPL_LIBDISK_SUPPORT 330 #define CONFIG_SPL_I2C_SUPPORT 331 #define CONFIG_SPL_LIBGENERIC_SUPPORT 332 #define CONFIG_SPL_MMC_SUPPORT 333 #define CONFIG_SPL_FAT_SUPPORT 334 #define CONFIG_SPL_SERIAL_SUPPORT 335 #define CONFIG_SPL_NAND_SUPPORT 336 #define CONFIG_SPL_NAND_BASE 337 #define CONFIG_SPL_NAND_DRIVERS 338 #define CONFIG_SPL_NAND_ECC 339 #define CONFIG_SPL_GPIO_SUPPORT 340 #define CONFIG_SPL_POWER_SUPPORT 341 #define CONFIG_SPL_OMAP3_ID_NAND 342 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 343 344 /* NAND boot config */ 345 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 346 #define CONFIG_SYS_NAND_PAGE_COUNT 64 347 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 348 #define CONFIG_SYS_NAND_OOBSIZE 64 349 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 350 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 351 /* 352 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 353 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 354 */ 355 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 356 10, 11, 12 } 357 #define CONFIG_SYS_NAND_ECCSIZE 512 358 #define CONFIG_SYS_NAND_ECCBYTES 3 359 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 360 361 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 362 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 363 364 #define CONFIG_SPL_TEXT_BASE 0x40200800 365 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 366 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 367 368 /* 369 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 370 * older x-loader implementations. And move the BSS area so that it 371 * doesn't overlap with TEXT_BASE. 372 */ 373 #define CONFIG_SYS_TEXT_BASE 0x80008000 374 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 375 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 376 377 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 378 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 379 380 #endif /* __CONFIG_H */ 381