1 /* 2 * (C) Copyright 2011 3 * CompuLab, Ltd. 4 * Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Based on omap3_beagle.h 8 * (C) Copyright 2006-2008 9 * Texas Instruments. 10 * Richard Woodruff <r-woodruff2@ti.com> 11 * Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc. 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* 37 * High Level Configuration Options 38 */ 39 #define CONFIG_OMAP 1 /* in a TI OMAP core */ 40 #define CONFIG_OMAP34XX 1 /* which is a 34XX */ 41 #define CONFIG_OMAP3430 1 /* which is in a 3430 */ 42 #define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */ 43 44 #define CONFIG_SYS_TEXT_BASE 0x80008000 45 46 #define CONFIG_SDRC /* The chip has SDRC controller */ 47 48 #include <asm/arch/cpu.h> /* get chip and board defs */ 49 #include <asm/arch/omap3.h> 50 51 /* 52 * Display CPU and Board information 53 */ 54 #define CONFIG_DISPLAY_CPUINFO 1 55 #define CONFIG_DISPLAY_BOARDINFO 1 56 57 /* Clock Defines */ 58 #define V_OSCK 26000000 /* Clock output from T2 */ 59 #define V_SCLK (V_OSCK >> 1) 60 61 #undef CONFIG_USE_IRQ /* no support for IRQs */ 62 #define CONFIG_MISC_INIT_R 63 64 #define CONFIG_OF_LIBFDT 1 65 /* 66 * The early kernel mapping on ARM currently only maps from the base of DRAM 67 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. 68 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, 69 * so that leaves DRAM base to DRAM base + 0x4000 available. 70 */ 71 #define CONFIG_SYS_BOOTMAPSZ 0x4000 72 73 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 74 #define CONFIG_SETUP_MEMORY_TAGS 1 75 #define CONFIG_INITRD_TAG 1 76 #define CONFIG_REVISION_TAG 1 77 78 /* 79 * Size of malloc() pool 80 */ 81 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 82 /* Sector */ 83 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 84 85 /* 86 * Hardware drivers 87 */ 88 89 /* 90 * NS16550 Configuration 91 */ 92 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 93 94 #define CONFIG_SYS_NS16550 95 #define CONFIG_SYS_NS16550_SERIAL 96 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 97 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 98 99 /* 100 * select serial console configuration 101 */ 102 #define CONFIG_CONS_INDEX 3 103 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 104 #define CONFIG_SERIAL3 3 /* UART3 */ 105 106 /* allow to overwrite serial and ethaddr */ 107 #define CONFIG_ENV_OVERWRITE 108 #define CONFIG_BAUDRATE 115200 109 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 110 115200} 111 #define CONFIG_GENERIC_MMC 1 112 #define CONFIG_MMC 1 113 #define CONFIG_OMAP_HSMMC 1 114 #define CONFIG_DOS_PARTITION 1 115 116 /* DDR - I use Micron DDR */ 117 #define CONFIG_OMAP3_MICRON_DDR 1 118 119 /* USB */ 120 #define CONFIG_MUSB_UDC 1 121 #define CONFIG_USB_OMAP3 1 122 #define CONFIG_TWL4030_USB 1 123 124 /* USB device configuration */ 125 #define CONFIG_USB_DEVICE 1 126 #define CONFIG_USB_TTY 1 127 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 128 129 /* commands to include */ 130 #include <config_cmd_default.h> 131 132 #define CONFIG_CMD_CACHE 133 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 134 #define CONFIG_CMD_FAT /* FAT support */ 135 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 136 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 137 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 138 #define MTDIDS_DEFAULT "nand0=nand" 139 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 140 "1920k(u-boot),128k(u-boot-env),"\ 141 "4m(kernel),-(fs)" 142 143 #define CONFIG_CMD_I2C /* I2C serial bus support */ 144 #define CONFIG_CMD_MMC /* MMC support */ 145 #define CONFIG_CMD_NAND /* NAND support */ 146 #define CONFIG_CMD_DHCP 147 #define CONFIG_CMD_PING 148 149 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 150 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 151 #undef CONFIG_CMD_IMLS /* List all found images */ 152 153 #define CONFIG_SYS_NO_FLASH 154 #define CONFIG_HARD_I2C 1 155 #define CONFIG_SYS_I2C_SPEED 100000 156 #define CONFIG_SYS_I2C_SLAVE 1 157 #define CONFIG_SYS_I2C_BUS 0 158 #define CONFIG_SYS_I2C_BUS_SELECT 1 159 #define CONFIG_DRIVER_OMAP34XX_I2C 1 160 161 /* 162 * TWL4030 163 */ 164 #define CONFIG_TWL4030_POWER 1 165 #define CONFIG_TWL4030_LED 1 166 167 /* 168 * Board NAND Info. 169 */ 170 #define CONFIG_SYS_NAND_QUIET_TEST 1 171 #define CONFIG_NAND_OMAP_GPMC 172 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 173 /* to access nand */ 174 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 175 /* to access nand at */ 176 /* CS0 */ 177 #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 178 179 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 180 /* devices */ 181 #define CONFIG_JFFS2_NAND 182 /* nand device jffs2 lives on */ 183 #define CONFIG_JFFS2_DEV "nand0" 184 /* start of jffs2 partition */ 185 #define CONFIG_JFFS2_PART_OFFSET 0x680000 186 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 187 /* partition */ 188 189 /* Environment information */ 190 #define CONFIG_BOOTDELAY 10 191 192 #define CONFIG_EXTRA_ENV_SETTINGS \ 193 "loadaddr=0x82000000\0" \ 194 "usbtty=cdc_acm\0" \ 195 "console=ttyS2,115200n8\0" \ 196 "mpurate=500\0" \ 197 "vram=12M\0" \ 198 "dvimode=1024x768MR-16@60\0" \ 199 "defaultdisplay=dvi\0" \ 200 "mmcdev=0\0" \ 201 "mmcroot=/dev/mmcblk0p2 rw\0" \ 202 "mmcrootfstype=ext3 rootwait\0" \ 203 "nandroot=/dev/mtdblock4 rw\0" \ 204 "nandrootfstype=jffs2\0" \ 205 "mmcargs=setenv bootargs console=${console} " \ 206 "mpurate=${mpurate} " \ 207 "vram=${vram} " \ 208 "omapfb.mode=dvi:${dvimode} " \ 209 "omapfb.debug=y " \ 210 "omapdss.def_disp=${defaultdisplay} " \ 211 "root=${mmcroot} " \ 212 "rootfstype=${mmcrootfstype}\0" \ 213 "nandargs=setenv bootargs console=${console} " \ 214 "mpurate=${mpurate} " \ 215 "vram=${vram} " \ 216 "omapfb.mode=dvi:${dvimode} " \ 217 "omapfb.debug=y " \ 218 "omapdss.def_disp=${defaultdisplay} " \ 219 "root=${nandroot} " \ 220 "rootfstype=${nandrootfstype}\0" \ 221 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 222 "bootscript=echo Running bootscript from mmc ...; " \ 223 "source ${loadaddr}\0" \ 224 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 225 "mmcboot=echo Booting from mmc ...; " \ 226 "run mmcargs; " \ 227 "bootm ${loadaddr}\0" \ 228 "nandboot=echo Booting from nand ...; " \ 229 "run nandargs; " \ 230 "nand read ${loadaddr} 280000 400000; " \ 231 "bootm ${loadaddr}\0" \ 232 233 #define CONFIG_BOOTCOMMAND \ 234 "if mmc rescan ${mmcdev}; then " \ 235 "if run loadbootscript; then " \ 236 "run bootscript; " \ 237 "else " \ 238 "if run loaduimage; then " \ 239 "run mmcboot; " \ 240 "else run nandboot; " \ 241 "fi; " \ 242 "fi; " \ 243 "else run nandboot; fi" 244 245 /* 246 * Miscellaneous configurable options 247 */ 248 #define CONFIG_AUTO_COMPLETE 249 #define CONFIG_CMDLINE_EDITING 250 #define CONFIG_TIMESTAMP 251 #define CONFIG_SYS_AUTOLOAD "no" 252 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 253 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 254 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 255 #define CONFIG_SYS_PROMPT "CM-T3x # " 256 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 257 /* Print Buffer Size */ 258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 259 sizeof(CONFIG_SYS_PROMPT) + 16) 260 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 261 /* Boot Argument Buffer Size */ 262 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 263 264 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 265 /* works on */ 266 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 267 0x01F00000) /* 31MB */ 268 269 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 270 /* load address */ 271 272 /* 273 * OMAP3 has 12 GP timers, they can be driven by the system clock 274 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 275 * This rate is divided by a local divisor. 276 */ 277 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 278 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 279 #define CONFIG_SYS_HZ 1000 280 281 /*----------------------------------------------------------------------- 282 * Stack sizes 283 * 284 * The stack sizes are set up in start.S using the settings below 285 */ 286 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 287 #ifdef CONFIG_USE_IRQ 288 #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 289 #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 290 #endif 291 292 /*----------------------------------------------------------------------- 293 * Physical Memory Map 294 */ 295 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 296 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 297 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 298 299 /* SDRAM Bank Allocation method */ 300 #define SDRC_R_B_C 1 301 302 /*----------------------------------------------------------------------- 303 * FLASH and environment organization 304 */ 305 306 /* **** PISMO SUPPORT *** */ 307 308 /* Configure the PISMO */ 309 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 310 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 311 312 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 313 314 #if defined(CONFIG_CMD_NAND) 315 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 316 #endif 317 318 /* Monitor at start of flash */ 319 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 320 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 321 322 #define CONFIG_ENV_IS_IN_NAND 1 323 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 324 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 325 326 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 327 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 328 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 329 330 #if defined(CONFIG_CMD_NET) 331 #define CONFIG_SMC911X 332 #define CONFIG_SMC911X_32_BIT 333 #define CM_T3X_SMC911X_BASE 0x2C000000 334 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 335 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 336 #endif /* (CONFIG_CMD_NET) */ 337 338 /* additions for new relocation code, must be added to all boards */ 339 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 340 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 341 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 342 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 343 CONFIG_SYS_INIT_RAM_SIZE - \ 344 GENERATED_GBL_DATA_SIZE) 345 346 /* Status LED */ 347 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 348 #define CONFIG_BOARD_SPECIFIC_LED 1 349 #define STATUS_LED_GREEN 0 350 #define STATUS_LED_BIT STATUS_LED_GREEN 351 #define STATUS_LED_STATE STATUS_LED_ON 352 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 353 #define STATUS_LED_BOOT STATUS_LED_BIT 354 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 355 356 /* GPIO banks */ 357 #ifdef CONFIG_STATUS_LED 358 #define CONFIG_OMAP3_GPIO_6 1 /* GPIO186 is in GPIO bank 6 */ 359 #endif 360 361 #endif /* __CONFIG_H */ 362