1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 /* Common ARM Erratas */ 29 #define CONFIG_ARM_ERRATA_454179 30 #define CONFIG_ARM_ERRATA_430973 31 #define CONFIG_ARM_ERRATA_621766 32 33 #define CONFIG_SDRC /* The chip has SDRC controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap.h> 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_INITRD_TAG 47 #define CONFIG_REVISION_TAG 48 #define CONFIG_SERIAL_TAG 49 50 /* 51 * Size of malloc() pool 52 */ 53 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 54 /* Sector */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 56 57 /* 58 * Hardware drivers 59 */ 60 61 /* 62 * NS16550 Configuration 63 */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 65 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 83 /* USB */ 84 #define CONFIG_USB_OMAP3 85 #define CONFIG_USB_EHCI 86 #define CONFIG_USB_EHCI_OMAP 87 #define CONFIG_USB_MUSB_UDC 88 #define CONFIG_TWL4030_USB 89 90 /* USB device configuration */ 91 #define CONFIG_USB_DEVICE 92 #define CONFIG_USB_TTY 93 94 /* commands to include */ 95 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 96 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 97 #define CONFIG_MTD_PARTITIONS 98 #define MTDIDS_DEFAULT "nand0=nand" 99 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 100 "1920k(u-boot),256k(u-boot-env),"\ 101 "4m(kernel),-(fs)" 102 103 #define CONFIG_CMD_NAND /* NAND support */ 104 105 #define CONFIG_SYS_NO_FLASH 106 #define CONFIG_SYS_I2C 107 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 108 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 109 #define CONFIG_SYS_I2C_OMAP34XX 110 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 112 #define CONFIG_SYS_I2C_EEPROM_BUS 0 113 #define CONFIG_I2C_MULTI_BUS 114 115 /* 116 * TWL4030 117 */ 118 #define CONFIG_TWL4030_POWER 119 #define CONFIG_TWL4030_LED 120 121 /* 122 * Board NAND Info. 123 */ 124 #define CONFIG_NAND_OMAP_GPMC 125 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 126 /* to access nand */ 127 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 128 /* to access nand at */ 129 /* CS0 */ 130 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 131 /* devices */ 132 133 /* Environment information */ 134 #define CONFIG_EXTRA_ENV_SETTINGS \ 135 "loadaddr=0x82000000\0" \ 136 "usbtty=cdc_acm\0" \ 137 "console=ttyO2,115200n8\0" \ 138 "mpurate=500\0" \ 139 "vram=12M\0" \ 140 "dvimode=1024x768MR-16@60\0" \ 141 "defaultdisplay=dvi\0" \ 142 "mmcdev=0\0" \ 143 "mmcroot=/dev/mmcblk0p2 rw\0" \ 144 "mmcrootfstype=ext4 rootwait\0" \ 145 "nandroot=/dev/mtdblock4 rw\0" \ 146 "nandrootfstype=ubifs\0" \ 147 "mmcargs=setenv bootargs console=${console} " \ 148 "mpurate=${mpurate} " \ 149 "vram=${vram} " \ 150 "omapfb.mode=dvi:${dvimode} " \ 151 "omapdss.def_disp=${defaultdisplay} " \ 152 "root=${mmcroot} " \ 153 "rootfstype=${mmcrootfstype}\0" \ 154 "nandargs=setenv bootargs console=${console} " \ 155 "mpurate=${mpurate} " \ 156 "vram=${vram} " \ 157 "omapfb.mode=dvi:${dvimode} " \ 158 "omapdss.def_disp=${defaultdisplay} " \ 159 "root=${nandroot} " \ 160 "rootfstype=${nandrootfstype}\0" \ 161 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 162 "bootscript=echo Running bootscript from mmc ...; " \ 163 "source ${loadaddr}\0" \ 164 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 165 "mmcboot=echo Booting from mmc ...; " \ 166 "run mmcargs; " \ 167 "bootm ${loadaddr}\0" \ 168 "nandboot=echo Booting from nand ...; " \ 169 "run nandargs; " \ 170 "nand read ${loadaddr} 2a0000 400000; " \ 171 "bootm ${loadaddr}\0" \ 172 173 #define CONFIG_BOOTCOMMAND \ 174 "mmc dev ${mmcdev}; if mmc rescan; then " \ 175 "if run loadbootscript; then " \ 176 "run bootscript; " \ 177 "else " \ 178 "if run loaduimage; then " \ 179 "run mmcboot; " \ 180 "else run nandboot; " \ 181 "fi; " \ 182 "fi; " \ 183 "else run nandboot; fi" 184 185 /* 186 * Miscellaneous configurable options 187 */ 188 #define CONFIG_AUTO_COMPLETE 189 #define CONFIG_CMDLINE_EDITING 190 #define CONFIG_TIMESTAMP 191 #define CONFIG_SYS_AUTOLOAD "no" 192 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 193 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 194 /* Print Buffer Size */ 195 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 196 sizeof(CONFIG_SYS_PROMPT) + 16) 197 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 198 /* Boot Argument Buffer Size */ 199 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 200 201 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 202 /* works on */ 203 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 204 0x01F00000) /* 31MB */ 205 206 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 207 /* load address */ 208 209 /* 210 * OMAP3 has 12 GP timers, they can be driven by the system clock 211 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 212 * This rate is divided by a local divisor. 213 */ 214 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 215 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 216 217 /*----------------------------------------------------------------------- 218 * Physical Memory Map 219 */ 220 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 221 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 222 223 /*----------------------------------------------------------------------- 224 * FLASH and environment organization 225 */ 226 227 /* **** PISMO SUPPORT *** */ 228 /* Monitor at start of flash */ 229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 230 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 231 232 #define CONFIG_ENV_IS_IN_NAND 233 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 234 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 235 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 236 237 #if defined(CONFIG_CMD_NET) 238 #define CONFIG_SMC911X 239 #define CONFIG_SMC911X_32_BIT 240 #define CM_T3X_SMC911X_BASE 0x2C000000 241 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 242 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 243 #endif /* (CONFIG_CMD_NET) */ 244 245 /* additions for new relocation code, must be added to all boards */ 246 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 247 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 248 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 250 CONFIG_SYS_INIT_RAM_SIZE - \ 251 GENERATED_GBL_DATA_SIZE) 252 253 /* Status LED */ 254 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 255 256 #define CONFIG_SPLASHIMAGE_GUARD 257 258 /* GPIO banks */ 259 #ifdef CONFIG_LED_STATUS 260 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 261 #endif 262 263 /* Display Configuration */ 264 #define CONFIG_OMAP3_GPIO_2 265 #define CONFIG_OMAP3_GPIO_5 266 #define CONFIG_VIDEO_OMAP3 267 #define LCD_BPP LCD_COLOR16 268 269 #define CONFIG_SPLASH_SCREEN 270 #define CONFIG_SPLASH_SOURCE 271 #define CONFIG_CMD_BMP 272 #define CONFIG_BMP_16BPP 273 #define CONFIG_SCF0403_LCD 274 275 #define CONFIG_OMAP3_SPI 276 277 /* Defines for SPL */ 278 #define CONFIG_SPL_FRAMEWORK 279 #define CONFIG_SPL_NAND_SIMPLE 280 281 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 282 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 283 284 #define CONFIG_SPL_BOARD_INIT 285 #define CONFIG_SPL_NAND_BASE 286 #define CONFIG_SPL_NAND_DRIVERS 287 #define CONFIG_SPL_NAND_ECC 288 #define CONFIG_SPL_OMAP3_ID_NAND 289 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 290 291 /* NAND boot config */ 292 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 293 #define CONFIG_SYS_NAND_PAGE_COUNT 64 294 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 295 #define CONFIG_SYS_NAND_OOBSIZE 64 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 297 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 298 /* 299 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 300 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 301 */ 302 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 303 10, 11, 12 } 304 #define CONFIG_SYS_NAND_ECCSIZE 512 305 #define CONFIG_SYS_NAND_ECCBYTES 3 306 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 307 308 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 309 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 310 311 #define CONFIG_SPL_TEXT_BASE 0x40200800 312 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 313 CONFIG_SPL_TEXT_BASE) 314 315 /* 316 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 317 * older x-loader implementations. And move the BSS area so that it 318 * doesn't overlap with TEXT_BASE. 319 */ 320 #define CONFIG_SYS_TEXT_BASE 0x80008000 321 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 322 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 323 324 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 325 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 326 327 /* EEPROM */ 328 #define CONFIG_CMD_EEPROM 329 #define CONFIG_ENV_EEPROM_IS_ON_I2C 330 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 332 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 333 #define CONFIG_SYS_EEPROM_SIZE 256 334 335 #define CONFIG_CMD_EEPROM_LAYOUT 336 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 337 338 #endif /* __CONFIG_H */ 339