1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 #define CONFIG_OMAP_COMMON 29 /* Common ARM Erratas */ 30 #define CONFIG_ARM_ERRATA_454179 31 #define CONFIG_ARM_ERRATA_430973 32 #define CONFIG_ARM_ERRATA_621766 33 34 #define CONFIG_SDRC /* The chip has SDRC controller */ 35 36 #include <asm/arch/cpu.h> /* get chip and board defs */ 37 #include <asm/arch/omap.h> 38 39 /* 40 * Display CPU and Board information 41 */ 42 #define CONFIG_DISPLAY_CPUINFO 43 #define CONFIG_DISPLAY_BOARDINFO 44 45 /* Clock Defines */ 46 #define V_OSCK 26000000 /* Clock output from T2 */ 47 #define V_SCLK (V_OSCK >> 1) 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_INITRD_TAG 54 #define CONFIG_REVISION_TAG 55 #define CONFIG_SERIAL_TAG 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 64 /* 65 * Hardware drivers 66 */ 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 76 77 /* 78 * select serial console configuration 79 */ 80 #define CONFIG_CONS_INDEX 3 81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 82 #define CONFIG_SERIAL3 3 /* UART3 */ 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 88 115200} 89 90 #define CONFIG_GENERIC_MMC 91 #define CONFIG_MMC 92 #define CONFIG_OMAP_HSMMC 93 #define CONFIG_DOS_PARTITION 94 95 /* USB */ 96 #define CONFIG_USB_OMAP3 97 #define CONFIG_USB_EHCI 98 #define CONFIG_USB_EHCI_OMAP 99 #define CONFIG_USB_STORAGE 100 #define CONFIG_USB_MUSB_UDC 101 #define CONFIG_TWL4030_USB 102 103 /* USB device configuration */ 104 #define CONFIG_USB_DEVICE 105 #define CONFIG_USB_TTY 106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 107 108 /* commands to include */ 109 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 110 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 111 #define CONFIG_MTD_PARTITIONS 112 #define MTDIDS_DEFAULT "nand0=nand" 113 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 114 "1920k(u-boot),256k(u-boot-env),"\ 115 "4m(kernel),-(fs)" 116 117 #define CONFIG_CMD_NAND /* NAND support */ 118 119 #define CONFIG_SYS_NO_FLASH 120 #define CONFIG_SYS_I2C 121 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 122 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 123 #define CONFIG_SYS_I2C_OMAP34XX 124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 126 #define CONFIG_SYS_I2C_EEPROM_BUS 0 127 #define CONFIG_I2C_MULTI_BUS 128 129 /* 130 * TWL4030 131 */ 132 #define CONFIG_TWL4030_POWER 133 #define CONFIG_TWL4030_LED 134 135 /* 136 * Board NAND Info. 137 */ 138 #define CONFIG_NAND_OMAP_GPMC 139 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 140 /* to access nand */ 141 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 142 /* to access nand at */ 143 /* CS0 */ 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 145 /* devices */ 146 147 /* Environment information */ 148 #define CONFIG_BOOTDELAY 3 149 #define CONFIG_ZERO_BOOTDELAY_CHECK 150 151 #define CONFIG_EXTRA_ENV_SETTINGS \ 152 "loadaddr=0x82000000\0" \ 153 "usbtty=cdc_acm\0" \ 154 "console=ttyO2,115200n8\0" \ 155 "mpurate=500\0" \ 156 "vram=12M\0" \ 157 "dvimode=1024x768MR-16@60\0" \ 158 "defaultdisplay=dvi\0" \ 159 "mmcdev=0\0" \ 160 "mmcroot=/dev/mmcblk0p2 rw\0" \ 161 "mmcrootfstype=ext4 rootwait\0" \ 162 "nandroot=/dev/mtdblock4 rw\0" \ 163 "nandrootfstype=ubifs\0" \ 164 "mmcargs=setenv bootargs console=${console} " \ 165 "mpurate=${mpurate} " \ 166 "vram=${vram} " \ 167 "omapfb.mode=dvi:${dvimode} " \ 168 "omapdss.def_disp=${defaultdisplay} " \ 169 "root=${mmcroot} " \ 170 "rootfstype=${mmcrootfstype}\0" \ 171 "nandargs=setenv bootargs console=${console} " \ 172 "mpurate=${mpurate} " \ 173 "vram=${vram} " \ 174 "omapfb.mode=dvi:${dvimode} " \ 175 "omapdss.def_disp=${defaultdisplay} " \ 176 "root=${nandroot} " \ 177 "rootfstype=${nandrootfstype}\0" \ 178 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 179 "bootscript=echo Running bootscript from mmc ...; " \ 180 "source ${loadaddr}\0" \ 181 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 182 "mmcboot=echo Booting from mmc ...; " \ 183 "run mmcargs; " \ 184 "bootm ${loadaddr}\0" \ 185 "nandboot=echo Booting from nand ...; " \ 186 "run nandargs; " \ 187 "nand read ${loadaddr} 2a0000 400000; " \ 188 "bootm ${loadaddr}\0" \ 189 190 #define CONFIG_BOOTCOMMAND \ 191 "mmc dev ${mmcdev}; if mmc rescan; then " \ 192 "if run loadbootscript; then " \ 193 "run bootscript; " \ 194 "else " \ 195 "if run loaduimage; then " \ 196 "run mmcboot; " \ 197 "else run nandboot; " \ 198 "fi; " \ 199 "fi; " \ 200 "else run nandboot; fi" 201 202 /* 203 * Miscellaneous configurable options 204 */ 205 #define CONFIG_AUTO_COMPLETE 206 #define CONFIG_CMDLINE_EDITING 207 #define CONFIG_TIMESTAMP 208 #define CONFIG_SYS_AUTOLOAD "no" 209 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 210 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 211 /* Print Buffer Size */ 212 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 213 sizeof(CONFIG_SYS_PROMPT) + 16) 214 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 215 /* Boot Argument Buffer Size */ 216 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 217 218 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 219 /* works on */ 220 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 221 0x01F00000) /* 31MB */ 222 223 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 224 /* load address */ 225 226 /* 227 * OMAP3 has 12 GP timers, they can be driven by the system clock 228 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 229 * This rate is divided by a local divisor. 230 */ 231 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 232 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 233 234 /*----------------------------------------------------------------------- 235 * Physical Memory Map 236 */ 237 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 238 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 239 240 /*----------------------------------------------------------------------- 241 * FLASH and environment organization 242 */ 243 244 /* **** PISMO SUPPORT *** */ 245 /* Monitor at start of flash */ 246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 247 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 248 249 #define CONFIG_ENV_IS_IN_NAND 250 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 251 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 252 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 253 254 #if defined(CONFIG_CMD_NET) 255 #define CONFIG_SMC911X 256 #define CONFIG_SMC911X_32_BIT 257 #define CM_T3X_SMC911X_BASE 0x2C000000 258 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 259 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 260 #endif /* (CONFIG_CMD_NET) */ 261 262 /* additions for new relocation code, must be added to all boards */ 263 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 264 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 265 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 266 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 267 CONFIG_SYS_INIT_RAM_SIZE - \ 268 GENERATED_GBL_DATA_SIZE) 269 270 /* Status LED */ 271 #define CONFIG_STATUS_LED /* Status LED enabled */ 272 #define CONFIG_BOARD_SPECIFIC_LED 273 #define CONFIG_GPIO_LED 274 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 275 #define GREEN_LED_DEV 0 276 #define STATUS_LED_BIT GREEN_LED_GPIO 277 #define STATUS_LED_STATE STATUS_LED_ON 278 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 279 #define STATUS_LED_BOOT GREEN_LED_DEV 280 281 #define CONFIG_SPLASHIMAGE_GUARD 282 283 /* GPIO banks */ 284 #ifdef CONFIG_STATUS_LED 285 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 286 #endif 287 288 /* Display Configuration */ 289 #define CONFIG_OMAP3_GPIO_2 290 #define CONFIG_OMAP3_GPIO_5 291 #define CONFIG_VIDEO_OMAP3 292 #define LCD_BPP LCD_COLOR16 293 294 #define CONFIG_LCD 295 #define CONFIG_SPLASH_SCREEN 296 #define CONFIG_SPLASH_SOURCE 297 #define CONFIG_CMD_BMP 298 #define CONFIG_BMP_16BPP 299 #define CONFIG_SCF0403_LCD 300 301 #define CONFIG_OMAP3_SPI 302 303 /* Defines for SPL */ 304 #define CONFIG_SPL_FRAMEWORK 305 #define CONFIG_SPL_NAND_SIMPLE 306 307 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 308 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 309 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 310 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 311 312 #define CONFIG_SPL_BOARD_INIT 313 #define CONFIG_SPL_LIBCOMMON_SUPPORT 314 #define CONFIG_SPL_LIBDISK_SUPPORT 315 #define CONFIG_SPL_I2C_SUPPORT 316 #define CONFIG_SPL_LIBGENERIC_SUPPORT 317 #define CONFIG_SPL_MMC_SUPPORT 318 #define CONFIG_SPL_FAT_SUPPORT 319 #define CONFIG_SPL_SERIAL_SUPPORT 320 #define CONFIG_SPL_NAND_SUPPORT 321 #define CONFIG_SPL_NAND_BASE 322 #define CONFIG_SPL_NAND_DRIVERS 323 #define CONFIG_SPL_NAND_ECC 324 #define CONFIG_SPL_GPIO_SUPPORT 325 #define CONFIG_SPL_POWER_SUPPORT 326 #define CONFIG_SPL_OMAP3_ID_NAND 327 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 328 329 /* NAND boot config */ 330 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 331 #define CONFIG_SYS_NAND_PAGE_COUNT 64 332 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 333 #define CONFIG_SYS_NAND_OOBSIZE 64 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 335 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 336 /* 337 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 338 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 339 */ 340 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 341 10, 11, 12 } 342 #define CONFIG_SYS_NAND_ECCSIZE 512 343 #define CONFIG_SYS_NAND_ECCBYTES 3 344 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 345 346 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 347 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 348 349 #define CONFIG_SPL_TEXT_BASE 0x40200800 350 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 351 352 /* 353 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 354 * older x-loader implementations. And move the BSS area so that it 355 * doesn't overlap with TEXT_BASE. 356 */ 357 #define CONFIG_SYS_TEXT_BASE 0x80008000 358 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 359 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 360 361 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 362 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 363 364 /* EEPROM */ 365 #define CONFIG_CMD_EEPROM 366 #define CONFIG_ENV_EEPROM_IS_ON_I2C 367 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 368 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 369 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 370 #define CONFIG_SYS_EEPROM_SIZE 256 371 372 #define CONFIG_CMD_EEPROM_LAYOUT 373 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 374 375 #endif /* __CONFIG_H */ 376