1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 #define CONFIG_OMAP_COMMON 27 /* Common ARM Erratas */ 28 #define CONFIG_ARM_ERRATA_454179 29 #define CONFIG_ARM_ERRATA_430973 30 #define CONFIG_ARM_ERRATA_621766 31 32 #define CONFIG_SDRC /* The chip has SDRC controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap.h> 36 37 /* 38 * Display CPU and Board information 39 */ 40 #define CONFIG_DISPLAY_CPUINFO 41 #define CONFIG_DISPLAY_BOARDINFO 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #define CONFIG_MISC_INIT_R 48 49 #define CONFIG_OF_LIBFDT 1 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_INITRD_TAG 54 #define CONFIG_REVISION_TAG 55 #define CONFIG_SERIAL_TAG 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 64 /* 65 * Hardware drivers 66 */ 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550 74 #define CONFIG_SYS_NS16550_SERIAL 75 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 76 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 77 78 /* 79 * select serial console configuration 80 */ 81 #define CONFIG_CONS_INDEX 3 82 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 83 #define CONFIG_SERIAL3 3 /* UART3 */ 84 85 /* allow to overwrite serial and ethaddr */ 86 #define CONFIG_ENV_OVERWRITE 87 #define CONFIG_BAUDRATE 115200 88 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 89 115200} 90 91 #define CONFIG_GENERIC_MMC 92 #define CONFIG_MMC 93 #define CONFIG_OMAP_HSMMC 94 #define CONFIG_DOS_PARTITION 95 96 /* USB */ 97 #define CONFIG_USB_OMAP3 98 #define CONFIG_USB_EHCI 99 #define CONFIG_USB_EHCI_OMAP 100 #define CONFIG_USB_STORAGE 101 #define CONFIG_USB_MUSB_UDC 102 #define CONFIG_TWL4030_USB 103 #define CONFIG_CMD_USB 104 105 /* USB device configuration */ 106 #define CONFIG_USB_DEVICE 107 #define CONFIG_USB_TTY 108 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 109 110 /* commands to include */ 111 #define CONFIG_CMD_CACHE 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 113 #define CONFIG_CMD_FAT /* FAT support */ 114 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 115 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 116 #define CONFIG_MTD_PARTITIONS 117 #define MTDIDS_DEFAULT "nand0=nand" 118 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 119 "1920k(u-boot),256k(u-boot-env),"\ 120 "4m(kernel),-(fs)" 121 122 #define CONFIG_CMD_I2C /* I2C serial bus support */ 123 #define CONFIG_CMD_MMC /* MMC support */ 124 #define CONFIG_CMD_NAND /* NAND support */ 125 #define CONFIG_CMD_DHCP 126 #define CONFIG_CMD_PING 127 128 129 #define CONFIG_SYS_NO_FLASH 130 #define CONFIG_SYS_I2C 131 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 132 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 133 #define CONFIG_SYS_I2C_OMAP34XX 134 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 135 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 136 #define CONFIG_SYS_I2C_EEPROM_BUS 0 137 #define CONFIG_I2C_MULTI_BUS 138 139 /* 140 * TWL4030 141 */ 142 #define CONFIG_TWL4030_POWER 143 #define CONFIG_TWL4030_LED 144 145 /* 146 * Board NAND Info. 147 */ 148 #define CONFIG_NAND_OMAP_GPMC 149 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 150 /* to access nand */ 151 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 152 /* to access nand at */ 153 /* CS0 */ 154 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 155 /* devices */ 156 157 /* Environment information */ 158 #define CONFIG_BOOTDELAY 3 159 #define CONFIG_ZERO_BOOTDELAY_CHECK 160 161 #define CONFIG_EXTRA_ENV_SETTINGS \ 162 "loadaddr=0x82000000\0" \ 163 "usbtty=cdc_acm\0" \ 164 "console=ttyO2,115200n8\0" \ 165 "mpurate=500\0" \ 166 "vram=12M\0" \ 167 "dvimode=1024x768MR-16@60\0" \ 168 "defaultdisplay=dvi\0" \ 169 "mmcdev=0\0" \ 170 "mmcroot=/dev/mmcblk0p2 rw\0" \ 171 "mmcrootfstype=ext4 rootwait\0" \ 172 "nandroot=/dev/mtdblock4 rw\0" \ 173 "nandrootfstype=ubifs\0" \ 174 "mmcargs=setenv bootargs console=${console} " \ 175 "mpurate=${mpurate} " \ 176 "vram=${vram} " \ 177 "omapfb.mode=dvi:${dvimode} " \ 178 "omapdss.def_disp=${defaultdisplay} " \ 179 "root=${mmcroot} " \ 180 "rootfstype=${mmcrootfstype}\0" \ 181 "nandargs=setenv bootargs console=${console} " \ 182 "mpurate=${mpurate} " \ 183 "vram=${vram} " \ 184 "omapfb.mode=dvi:${dvimode} " \ 185 "omapdss.def_disp=${defaultdisplay} " \ 186 "root=${nandroot} " \ 187 "rootfstype=${nandrootfstype}\0" \ 188 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 189 "bootscript=echo Running bootscript from mmc ...; " \ 190 "source ${loadaddr}\0" \ 191 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 192 "mmcboot=echo Booting from mmc ...; " \ 193 "run mmcargs; " \ 194 "bootm ${loadaddr}\0" \ 195 "nandboot=echo Booting from nand ...; " \ 196 "run nandargs; " \ 197 "nand read ${loadaddr} 2a0000 400000; " \ 198 "bootm ${loadaddr}\0" \ 199 200 #define CONFIG_CMD_BOOTZ 201 #define CONFIG_BOOTCOMMAND \ 202 "mmc dev ${mmcdev}; if mmc rescan; then " \ 203 "if run loadbootscript; then " \ 204 "run bootscript; " \ 205 "else " \ 206 "if run loaduimage; then " \ 207 "run mmcboot; " \ 208 "else run nandboot; " \ 209 "fi; " \ 210 "fi; " \ 211 "else run nandboot; fi" 212 213 /* 214 * Miscellaneous configurable options 215 */ 216 #define CONFIG_AUTO_COMPLETE 217 #define CONFIG_CMDLINE_EDITING 218 #define CONFIG_TIMESTAMP 219 #define CONFIG_SYS_AUTOLOAD "no" 220 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 221 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 222 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 223 /* Print Buffer Size */ 224 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 225 sizeof(CONFIG_SYS_PROMPT) + 16) 226 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 227 /* Boot Argument Buffer Size */ 228 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 229 230 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 231 /* works on */ 232 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 233 0x01F00000) /* 31MB */ 234 235 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 236 /* load address */ 237 238 /* 239 * OMAP3 has 12 GP timers, they can be driven by the system clock 240 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 241 * This rate is divided by a local divisor. 242 */ 243 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 244 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 245 246 /*----------------------------------------------------------------------- 247 * Physical Memory Map 248 */ 249 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 250 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 251 252 /*----------------------------------------------------------------------- 253 * FLASH and environment organization 254 */ 255 256 /* **** PISMO SUPPORT *** */ 257 /* Monitor at start of flash */ 258 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 259 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 260 261 #define CONFIG_ENV_IS_IN_NAND 262 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 263 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 264 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 265 266 #if defined(CONFIG_CMD_NET) 267 #define CONFIG_SMC911X 268 #define CONFIG_SMC911X_32_BIT 269 #define CM_T3X_SMC911X_BASE 0x2C000000 270 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 271 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 272 #endif /* (CONFIG_CMD_NET) */ 273 274 /* additions for new relocation code, must be added to all boards */ 275 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 276 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 277 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 279 CONFIG_SYS_INIT_RAM_SIZE - \ 280 GENERATED_GBL_DATA_SIZE) 281 282 /* Status LED */ 283 #define CONFIG_STATUS_LED /* Status LED enabled */ 284 #define CONFIG_BOARD_SPECIFIC_LED 285 #define CONFIG_GPIO_LED 286 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 287 #define GREEN_LED_DEV 0 288 #define STATUS_LED_BIT GREEN_LED_GPIO 289 #define STATUS_LED_STATE STATUS_LED_ON 290 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 291 #define STATUS_LED_BOOT GREEN_LED_DEV 292 293 #define CONFIG_SPLASHIMAGE_GUARD 294 295 /* GPIO banks */ 296 #ifdef CONFIG_STATUS_LED 297 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 298 #endif 299 300 /* Display Configuration */ 301 #define CONFIG_OMAP3_GPIO_2 302 #define CONFIG_OMAP3_GPIO_5 303 #define CONFIG_VIDEO_OMAP3 304 #define LCD_BPP LCD_COLOR16 305 306 #define CONFIG_LCD 307 #define CONFIG_SPLASH_SCREEN 308 #define CONFIG_SPLASH_SOURCE 309 #define CONFIG_CMD_BMP 310 #define CONFIG_BMP_16BPP 311 #define CONFIG_SCF0403_LCD 312 313 #define CONFIG_OMAP3_SPI 314 315 /* Defines for SPL */ 316 #define CONFIG_SPL_FRAMEWORK 317 #define CONFIG_SPL_NAND_SIMPLE 318 319 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 320 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 321 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 322 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 323 324 #define CONFIG_SPL_BOARD_INIT 325 #define CONFIG_SPL_LIBCOMMON_SUPPORT 326 #define CONFIG_SPL_LIBDISK_SUPPORT 327 #define CONFIG_SPL_I2C_SUPPORT 328 #define CONFIG_SPL_LIBGENERIC_SUPPORT 329 #define CONFIG_SPL_MMC_SUPPORT 330 #define CONFIG_SPL_FAT_SUPPORT 331 #define CONFIG_SPL_SERIAL_SUPPORT 332 #define CONFIG_SPL_NAND_SUPPORT 333 #define CONFIG_SPL_NAND_BASE 334 #define CONFIG_SPL_NAND_DRIVERS 335 #define CONFIG_SPL_NAND_ECC 336 #define CONFIG_SPL_GPIO_SUPPORT 337 #define CONFIG_SPL_POWER_SUPPORT 338 #define CONFIG_SPL_OMAP3_ID_NAND 339 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 340 341 /* NAND boot config */ 342 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 343 #define CONFIG_SYS_NAND_PAGE_COUNT 64 344 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 345 #define CONFIG_SYS_NAND_OOBSIZE 64 346 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 347 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 348 /* 349 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 350 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 351 */ 352 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 353 10, 11, 12 } 354 #define CONFIG_SYS_NAND_ECCSIZE 512 355 #define CONFIG_SYS_NAND_ECCBYTES 3 356 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 357 358 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 359 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 360 361 #define CONFIG_SPL_TEXT_BASE 0x40200800 362 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 363 364 /* 365 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 366 * older x-loader implementations. And move the BSS area so that it 367 * doesn't overlap with TEXT_BASE. 368 */ 369 #define CONFIG_SYS_TEXT_BASE 0x80008000 370 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 371 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 372 373 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 374 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 375 376 #endif /* __CONFIG_H */ 377