1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2011 CompuLab, Ltd. 4 * Mike Rapoport <mike@compulab.co.il> 5 * Igor Grinberg <grinberg@compulab.co.il> 6 * 7 * Based on omap3_beagle.h 8 * (C) Copyright 2006-2008 9 * Texas Instruments. 10 * Richard Woodruff <r-woodruff2@ti.com> 11 * Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 #define CONFIG_SYS_CACHELINE_SIZE 64 20 21 /* 22 * High Level Configuration Options 23 */ 24 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 #include <asm/arch/omap.h> 28 29 /* Clock Defines */ 30 #define V_OSCK 26000000 /* Clock output from T2 */ 31 #define V_SCLK (V_OSCK >> 1) 32 33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 34 #define CONFIG_SETUP_MEMORY_TAGS 35 #define CONFIG_INITRD_TAG 36 #define CONFIG_REVISION_TAG 37 #define CONFIG_SERIAL_TAG 38 39 /* 40 * Size of malloc() pool 41 */ 42 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 43 /* Sector */ 44 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 54 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 57 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 58 59 /* 60 * select serial console configuration 61 */ 62 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 63 #define CONFIG_SERIAL3 3 /* UART3 */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 70 /* USB device configuration */ 71 #define CONFIG_USB_DEVICE 72 #define CONFIG_USB_TTY 73 74 /* commands to include */ 75 76 #define CONFIG_SYS_I2C 77 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 78 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 79 #define CONFIG_SYS_I2C_EEPROM_BUS 0 80 #define CONFIG_I2C_MULTI_BUS 81 82 /* 83 * TWL4030 84 */ 85 #define CONFIG_TWL4030_LED 86 87 /* 88 * Board NAND Info. 89 */ 90 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 91 /* to access nand at */ 92 /* CS0 */ 93 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 94 /* devices */ 95 96 /* Environment information */ 97 #define CONFIG_EXTRA_ENV_SETTINGS \ 98 "loadaddr=0x82000000\0" \ 99 "usbtty=cdc_acm\0" \ 100 "console=ttyO2,115200n8\0" \ 101 "mpurate=500\0" \ 102 "vram=12M\0" \ 103 "dvimode=1024x768MR-16@60\0" \ 104 "defaultdisplay=dvi\0" \ 105 "mmcdev=0\0" \ 106 "mmcroot=/dev/mmcblk0p2 rw\0" \ 107 "mmcrootfstype=ext4 rootwait\0" \ 108 "nandroot=/dev/mtdblock4 rw\0" \ 109 "nandrootfstype=ubifs\0" \ 110 "mmcargs=setenv bootargs console=${console} " \ 111 "mpurate=${mpurate} " \ 112 "vram=${vram} " \ 113 "omapfb.mode=dvi:${dvimode} " \ 114 "omapdss.def_disp=${defaultdisplay} " \ 115 "root=${mmcroot} " \ 116 "rootfstype=${mmcrootfstype}\0" \ 117 "nandargs=setenv bootargs console=${console} " \ 118 "mpurate=${mpurate} " \ 119 "vram=${vram} " \ 120 "omapfb.mode=dvi:${dvimode} " \ 121 "omapdss.def_disp=${defaultdisplay} " \ 122 "root=${nandroot} " \ 123 "rootfstype=${nandrootfstype}\0" \ 124 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 125 "bootscript=echo Running bootscript from mmc ...; " \ 126 "source ${loadaddr}\0" \ 127 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 128 "mmcboot=echo Booting from mmc ...; " \ 129 "run mmcargs; " \ 130 "bootm ${loadaddr}\0" \ 131 "nandboot=echo Booting from nand ...; " \ 132 "run nandargs; " \ 133 "nand read ${loadaddr} 2a0000 400000; " \ 134 "bootm ${loadaddr}\0" \ 135 136 #define CONFIG_BOOTCOMMAND \ 137 "mmc dev ${mmcdev}; if mmc rescan; then " \ 138 "if run loadbootscript; then " \ 139 "run bootscript; " \ 140 "else " \ 141 "if run loaduimage; then " \ 142 "run mmcboot; " \ 143 "else run nandboot; " \ 144 "fi; " \ 145 "fi; " \ 146 "else run nandboot; fi" 147 148 /* 149 * Miscellaneous configurable options 150 */ 151 #define CONFIG_TIMESTAMP 152 #define CONFIG_SYS_AUTOLOAD "no" 153 154 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 155 /* works on */ 156 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 157 0x01F00000) /* 31MB */ 158 159 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 160 /* load address */ 161 162 /* 163 * OMAP3 has 12 GP timers, they can be driven by the system clock 164 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 165 * This rate is divided by a local divisor. 166 */ 167 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 168 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 169 170 /*----------------------------------------------------------------------- 171 * Physical Memory Map 172 */ 173 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 174 175 /*----------------------------------------------------------------------- 176 * FLASH and environment organization 177 */ 178 179 /* **** PISMO SUPPORT *** */ 180 /* Monitor at start of flash */ 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 182 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 183 184 #define CONFIG_ENV_OFFSET 0x260000 185 #define CONFIG_ENV_ADDR 0x260000 186 187 /* additions for new relocation code, must be added to all boards */ 188 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 189 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 190 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 191 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 192 CONFIG_SYS_INIT_RAM_SIZE - \ 193 GENERATED_GBL_DATA_SIZE) 194 195 /* Status LED */ 196 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 197 198 #define CONFIG_SPLASHIMAGE_GUARD 199 200 /* Display Configuration */ 201 #define LCD_BPP LCD_COLOR16 202 203 #define CONFIG_SPLASH_SCREEN 204 #define CONFIG_SPLASH_SOURCE 205 #define CONFIG_BMP_16BPP 206 #define CONFIG_SCF0403_LCD 207 208 /* Defines for SPL */ 209 210 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 211 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 212 213 #define CONFIG_SPL_NAND_BASE 214 #define CONFIG_SPL_NAND_DRIVERS 215 #define CONFIG_SPL_NAND_ECC 216 217 /* NAND boot config */ 218 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 219 #define CONFIG_SYS_NAND_PAGE_COUNT 64 220 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 221 #define CONFIG_SYS_NAND_OOBSIZE 64 222 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 223 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 224 /* 225 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 226 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 227 */ 228 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 229 10, 11, 12 } 230 #define CONFIG_SYS_NAND_ECCSIZE 512 231 #define CONFIG_SYS_NAND_ECCBYTES 3 232 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 233 234 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 236 237 #define CONFIG_SPL_TEXT_BASE 0x40200800 238 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 239 CONFIG_SPL_TEXT_BASE) 240 241 /* 242 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 243 * older x-loader implementations. And move the BSS area so that it 244 * doesn't overlap with TEXT_BASE. 245 */ 246 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 247 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 248 249 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 250 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 251 252 /* EEPROM */ 253 #define CONFIG_ENV_EEPROM_IS_ON_I2C 254 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 257 #define CONFIG_SYS_EEPROM_SIZE 256 258 259 #endif /* __CONFIG_H */ 260