1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 #define CONFIG_SYS_CACHELINE_SIZE 64 21 22 /* 23 * High Level Configuration Options 24 */ 25 #define CONFIG_OMAP /* in a TI OMAP core */ 26 #define CONFIG_OMAP_GPIO 27 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28 /* Common ARM Erratas */ 29 #define CONFIG_ARM_ERRATA_454179 30 #define CONFIG_ARM_ERRATA_430973 31 #define CONFIG_ARM_ERRATA_621766 32 33 #define CONFIG_SDRC /* The chip has SDRC controller */ 34 35 #include <asm/arch/cpu.h> /* get chip and board defs */ 36 #include <asm/arch/omap.h> 37 38 /* Clock Defines */ 39 #define V_OSCK 26000000 /* Clock output from T2 */ 40 #define V_SCLK (V_OSCK >> 1) 41 42 #define CONFIG_MISC_INIT_R 43 44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_INITRD_TAG 47 #define CONFIG_REVISION_TAG 48 #define CONFIG_SERIAL_TAG 49 50 /* 51 * Size of malloc() pool 52 */ 53 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 54 /* Sector */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 56 57 /* 58 * Hardware drivers 59 */ 60 61 /* 62 * NS16550 Configuration 63 */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 65 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 #define CONFIG_SERIAL3 3 /* UART3 */ 76 77 /* allow to overwrite serial and ethaddr */ 78 #define CONFIG_ENV_OVERWRITE 79 #define CONFIG_BAUDRATE 115200 80 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 81 115200} 82 83 #define CONFIG_GENERIC_MMC 84 #define CONFIG_DOS_PARTITION 85 86 /* USB */ 87 #define CONFIG_USB_OMAP3 88 #define CONFIG_USB_EHCI 89 #define CONFIG_USB_EHCI_OMAP 90 #define CONFIG_USB_MUSB_UDC 91 #define CONFIG_TWL4030_USB 92 93 /* USB device configuration */ 94 #define CONFIG_USB_DEVICE 95 #define CONFIG_USB_TTY 96 97 /* commands to include */ 98 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 100 #define CONFIG_MTD_PARTITIONS 101 #define MTDIDS_DEFAULT "nand0=nand" 102 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 103 "1920k(u-boot),256k(u-boot-env),"\ 104 "4m(kernel),-(fs)" 105 106 #define CONFIG_CMD_NAND /* NAND support */ 107 108 #define CONFIG_SYS_NO_FLASH 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 111 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 112 #define CONFIG_SYS_I2C_OMAP34XX 113 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 115 #define CONFIG_SYS_I2C_EEPROM_BUS 0 116 #define CONFIG_I2C_MULTI_BUS 117 118 /* 119 * TWL4030 120 */ 121 #define CONFIG_TWL4030_POWER 122 #define CONFIG_TWL4030_LED 123 124 /* 125 * Board NAND Info. 126 */ 127 #define CONFIG_NAND_OMAP_GPMC 128 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 129 /* to access nand */ 130 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 131 /* to access nand at */ 132 /* CS0 */ 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 134 /* devices */ 135 136 /* Environment information */ 137 #define CONFIG_EXTRA_ENV_SETTINGS \ 138 "loadaddr=0x82000000\0" \ 139 "usbtty=cdc_acm\0" \ 140 "console=ttyO2,115200n8\0" \ 141 "mpurate=500\0" \ 142 "vram=12M\0" \ 143 "dvimode=1024x768MR-16@60\0" \ 144 "defaultdisplay=dvi\0" \ 145 "mmcdev=0\0" \ 146 "mmcroot=/dev/mmcblk0p2 rw\0" \ 147 "mmcrootfstype=ext4 rootwait\0" \ 148 "nandroot=/dev/mtdblock4 rw\0" \ 149 "nandrootfstype=ubifs\0" \ 150 "mmcargs=setenv bootargs console=${console} " \ 151 "mpurate=${mpurate} " \ 152 "vram=${vram} " \ 153 "omapfb.mode=dvi:${dvimode} " \ 154 "omapdss.def_disp=${defaultdisplay} " \ 155 "root=${mmcroot} " \ 156 "rootfstype=${mmcrootfstype}\0" \ 157 "nandargs=setenv bootargs console=${console} " \ 158 "mpurate=${mpurate} " \ 159 "vram=${vram} " \ 160 "omapfb.mode=dvi:${dvimode} " \ 161 "omapdss.def_disp=${defaultdisplay} " \ 162 "root=${nandroot} " \ 163 "rootfstype=${nandrootfstype}\0" \ 164 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 165 "bootscript=echo Running bootscript from mmc ...; " \ 166 "source ${loadaddr}\0" \ 167 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 168 "mmcboot=echo Booting from mmc ...; " \ 169 "run mmcargs; " \ 170 "bootm ${loadaddr}\0" \ 171 "nandboot=echo Booting from nand ...; " \ 172 "run nandargs; " \ 173 "nand read ${loadaddr} 2a0000 400000; " \ 174 "bootm ${loadaddr}\0" \ 175 176 #define CONFIG_BOOTCOMMAND \ 177 "mmc dev ${mmcdev}; if mmc rescan; then " \ 178 "if run loadbootscript; then " \ 179 "run bootscript; " \ 180 "else " \ 181 "if run loaduimage; then " \ 182 "run mmcboot; " \ 183 "else run nandboot; " \ 184 "fi; " \ 185 "fi; " \ 186 "else run nandboot; fi" 187 188 /* 189 * Miscellaneous configurable options 190 */ 191 #define CONFIG_AUTO_COMPLETE 192 #define CONFIG_CMDLINE_EDITING 193 #define CONFIG_TIMESTAMP 194 #define CONFIG_SYS_AUTOLOAD "no" 195 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 196 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 197 /* Print Buffer Size */ 198 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 199 sizeof(CONFIG_SYS_PROMPT) + 16) 200 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 201 /* Boot Argument Buffer Size */ 202 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 203 204 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 205 /* works on */ 206 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 207 0x01F00000) /* 31MB */ 208 209 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 210 /* load address */ 211 212 /* 213 * OMAP3 has 12 GP timers, they can be driven by the system clock 214 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 215 * This rate is divided by a local divisor. 216 */ 217 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 218 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 219 220 /*----------------------------------------------------------------------- 221 * Physical Memory Map 222 */ 223 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 224 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 225 226 /*----------------------------------------------------------------------- 227 * FLASH and environment organization 228 */ 229 230 /* **** PISMO SUPPORT *** */ 231 /* Monitor at start of flash */ 232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 233 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 234 235 #define CONFIG_ENV_IS_IN_NAND 236 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 237 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 238 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 239 240 #if defined(CONFIG_CMD_NET) 241 #define CONFIG_SMC911X 242 #define CONFIG_SMC911X_32_BIT 243 #define CM_T3X_SMC911X_BASE 0x2C000000 244 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 245 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 246 #endif /* (CONFIG_CMD_NET) */ 247 248 /* additions for new relocation code, must be added to all boards */ 249 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 250 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 251 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 253 CONFIG_SYS_INIT_RAM_SIZE - \ 254 GENERATED_GBL_DATA_SIZE) 255 256 /* Status LED */ 257 #define CONFIG_STATUS_LED /* Status LED enabled */ 258 #define CONFIG_BOARD_SPECIFIC_LED 259 #define CONFIG_GPIO_LED 260 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 261 #define GREEN_LED_DEV 0 262 #define STATUS_LED_BIT GREEN_LED_GPIO 263 #define STATUS_LED_STATE STATUS_LED_ON 264 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 265 #define STATUS_LED_BOOT GREEN_LED_DEV 266 267 #define CONFIG_SPLASHIMAGE_GUARD 268 269 /* GPIO banks */ 270 #ifdef CONFIG_STATUS_LED 271 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 272 #endif 273 274 /* Display Configuration */ 275 #define CONFIG_OMAP3_GPIO_2 276 #define CONFIG_OMAP3_GPIO_5 277 #define CONFIG_VIDEO_OMAP3 278 #define LCD_BPP LCD_COLOR16 279 280 #define CONFIG_SPLASH_SCREEN 281 #define CONFIG_SPLASH_SOURCE 282 #define CONFIG_CMD_BMP 283 #define CONFIG_BMP_16BPP 284 #define CONFIG_SCF0403_LCD 285 286 #define CONFIG_OMAP3_SPI 287 288 /* Defines for SPL */ 289 #define CONFIG_SPL_FRAMEWORK 290 #define CONFIG_SPL_NAND_SIMPLE 291 292 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 293 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 294 295 #define CONFIG_SPL_BOARD_INIT 296 #define CONFIG_SPL_NAND_BASE 297 #define CONFIG_SPL_NAND_DRIVERS 298 #define CONFIG_SPL_NAND_ECC 299 #define CONFIG_SPL_OMAP3_ID_NAND 300 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 301 302 /* NAND boot config */ 303 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 304 #define CONFIG_SYS_NAND_PAGE_COUNT 64 305 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 306 #define CONFIG_SYS_NAND_OOBSIZE 64 307 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 308 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 309 /* 310 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 311 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 312 */ 313 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 314 10, 11, 12 } 315 #define CONFIG_SYS_NAND_ECCSIZE 512 316 #define CONFIG_SYS_NAND_ECCBYTES 3 317 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 318 319 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 320 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 321 322 #define CONFIG_SPL_TEXT_BASE 0x40200800 323 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 324 CONFIG_SPL_TEXT_BASE) 325 326 /* 327 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 328 * older x-loader implementations. And move the BSS area so that it 329 * doesn't overlap with TEXT_BASE. 330 */ 331 #define CONFIG_SYS_TEXT_BASE 0x80008000 332 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 333 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 334 335 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 336 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 337 338 /* EEPROM */ 339 #define CONFIG_CMD_EEPROM 340 #define CONFIG_ENV_EEPROM_IS_ON_I2C 341 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 342 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 343 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 344 #define CONFIG_SYS_EEPROM_SIZE 256 345 346 #define CONFIG_CMD_EEPROM_LAYOUT 347 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 348 349 #endif /* __CONFIG_H */ 350