1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CMD_GPIO 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 27 #define CONFIG_OMAP_COMMON 28 #define CONFIG_SYS_GENERIC_BOARD 29 30 #define CONFIG_SDRC /* The chip has SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_OF_LIBFDT 1 48 49 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 50 #define CONFIG_SETUP_MEMORY_TAGS 51 #define CONFIG_INITRD_TAG 52 #define CONFIG_REVISION_TAG 53 #define CONFIG_SERIAL_TAG 54 55 /* 56 * Size of malloc() pool 57 */ 58 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 59 /* Sector */ 60 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61 62 /* 63 * Hardware drivers 64 */ 65 66 /* 67 * NS16550 Configuration 68 */ 69 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 70 71 #define CONFIG_SYS_NS16550 72 #define CONFIG_SYS_NS16550_SERIAL 73 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 74 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 75 76 /* 77 * select serial console configuration 78 */ 79 #define CONFIG_CONS_INDEX 3 80 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 81 #define CONFIG_SERIAL3 3 /* UART3 */ 82 83 /* allow to overwrite serial and ethaddr */ 84 #define CONFIG_ENV_OVERWRITE 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 87 115200} 88 89 #define CONFIG_GENERIC_MMC 90 #define CONFIG_MMC 91 #define CONFIG_OMAP_HSMMC 92 #define CONFIG_DOS_PARTITION 93 94 /* USB */ 95 #define CONFIG_USB_OMAP3 96 #define CONFIG_USB_EHCI 97 #define CONFIG_USB_EHCI_OMAP 98 #define CONFIG_USB_STORAGE 99 #define CONFIG_MUSB_UDC 100 #define CONFIG_TWL4030_USB 101 #define CONFIG_CMD_USB 102 103 /* USB device configuration */ 104 #define CONFIG_USB_DEVICE 105 #define CONFIG_USB_TTY 106 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 107 108 /* commands to include */ 109 #include <config_cmd_default.h> 110 111 #define CONFIG_CMD_CACHE 112 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 113 #define CONFIG_CMD_FAT /* FAT support */ 114 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 115 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 116 #define CONFIG_MTD_PARTITIONS 117 #define MTDIDS_DEFAULT "nand0=nand" 118 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 119 "1920k(u-boot),256k(u-boot-env),"\ 120 "4m(kernel),-(fs)" 121 122 #define CONFIG_CMD_I2C /* I2C serial bus support */ 123 #define CONFIG_CMD_MMC /* MMC support */ 124 #define CONFIG_CMD_NAND /* NAND support */ 125 #define CONFIG_CMD_DHCP 126 #define CONFIG_CMD_PING 127 128 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 129 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 130 #undef CONFIG_CMD_IMLS /* List all found images */ 131 132 #define CONFIG_SYS_NO_FLASH 133 #define CONFIG_SYS_I2C 134 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 135 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 136 #define CONFIG_SYS_I2C_OMAP34XX 137 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 138 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 139 #define CONFIG_SYS_I2C_EEPROM_BUS 0 140 #define CONFIG_I2C_MULTI_BUS 141 142 /* 143 * TWL4030 144 */ 145 #define CONFIG_TWL4030_POWER 146 #define CONFIG_TWL4030_LED 147 148 /* 149 * Board NAND Info. 150 */ 151 #define CONFIG_SYS_NAND_QUIET_TEST 152 #define CONFIG_NAND_OMAP_GPMC 153 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 154 /* to access nand */ 155 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 156 /* to access nand at */ 157 /* CS0 */ 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 159 /* devices */ 160 161 /* Environment information */ 162 #define CONFIG_BOOTDELAY 3 163 #define CONFIG_ZERO_BOOTDELAY_CHECK 164 165 #define CONFIG_EXTRA_ENV_SETTINGS \ 166 "loadaddr=0x82000000\0" \ 167 "usbtty=cdc_acm\0" \ 168 "console=ttyO2,115200n8\0" \ 169 "mpurate=500\0" \ 170 "vram=12M\0" \ 171 "dvimode=1024x768MR-16@60\0" \ 172 "defaultdisplay=dvi\0" \ 173 "mmcdev=0\0" \ 174 "mmcroot=/dev/mmcblk0p2 rw\0" \ 175 "mmcrootfstype=ext4 rootwait\0" \ 176 "nandroot=/dev/mtdblock4 rw\0" \ 177 "nandrootfstype=ubifs\0" \ 178 "mmcargs=setenv bootargs console=${console} " \ 179 "mpurate=${mpurate} " \ 180 "vram=${vram} " \ 181 "omapfb.mode=dvi:${dvimode} " \ 182 "omapdss.def_disp=${defaultdisplay} " \ 183 "root=${mmcroot} " \ 184 "rootfstype=${mmcrootfstype}\0" \ 185 "nandargs=setenv bootargs console=${console} " \ 186 "mpurate=${mpurate} " \ 187 "vram=${vram} " \ 188 "omapfb.mode=dvi:${dvimode} " \ 189 "omapdss.def_disp=${defaultdisplay} " \ 190 "root=${nandroot} " \ 191 "rootfstype=${nandrootfstype}\0" \ 192 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 193 "bootscript=echo Running bootscript from mmc ...; " \ 194 "source ${loadaddr}\0" \ 195 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 196 "mmcboot=echo Booting from mmc ...; " \ 197 "run mmcargs; " \ 198 "bootm ${loadaddr}\0" \ 199 "nandboot=echo Booting from nand ...; " \ 200 "run nandargs; " \ 201 "nand read ${loadaddr} 2a0000 400000; " \ 202 "bootm ${loadaddr}\0" \ 203 204 #define CONFIG_CMD_BOOTZ 205 #define CONFIG_BOOTCOMMAND \ 206 "mmc dev ${mmcdev}; if mmc rescan; then " \ 207 "if run loadbootscript; then " \ 208 "run bootscript; " \ 209 "else " \ 210 "if run loaduimage; then " \ 211 "run mmcboot; " \ 212 "else run nandboot; " \ 213 "fi; " \ 214 "fi; " \ 215 "else run nandboot; fi" 216 217 /* 218 * Miscellaneous configurable options 219 */ 220 #define CONFIG_AUTO_COMPLETE 221 #define CONFIG_CMDLINE_EDITING 222 #define CONFIG_TIMESTAMP 223 #define CONFIG_SYS_AUTOLOAD "no" 224 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 225 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 226 #define CONFIG_SYS_PROMPT "CM-T3x # " 227 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 228 /* Print Buffer Size */ 229 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 230 sizeof(CONFIG_SYS_PROMPT) + 16) 231 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 232 /* Boot Argument Buffer Size */ 233 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 234 235 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 236 /* works on */ 237 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 238 0x01F00000) /* 31MB */ 239 240 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 241 /* load address */ 242 243 /* 244 * OMAP3 has 12 GP timers, they can be driven by the system clock 245 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 246 * This rate is divided by a local divisor. 247 */ 248 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 249 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 250 251 /*----------------------------------------------------------------------- 252 * Physical Memory Map 253 */ 254 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 255 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 256 257 /*----------------------------------------------------------------------- 258 * FLASH and environment organization 259 */ 260 261 /* **** PISMO SUPPORT *** */ 262 /* Monitor at start of flash */ 263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 264 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 265 266 #define CONFIG_ENV_IS_IN_NAND 267 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 268 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 269 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 270 271 #if defined(CONFIG_CMD_NET) 272 #define CONFIG_SMC911X 273 #define CONFIG_SMC911X_32_BIT 274 #define CM_T3X_SMC911X_BASE 0x2C000000 275 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 276 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 277 #endif /* (CONFIG_CMD_NET) */ 278 279 /* additions for new relocation code, must be added to all boards */ 280 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 281 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 282 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 283 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 284 CONFIG_SYS_INIT_RAM_SIZE - \ 285 GENERATED_GBL_DATA_SIZE) 286 287 /* Status LED */ 288 #define CONFIG_STATUS_LED /* Status LED enabled */ 289 #define CONFIG_BOARD_SPECIFIC_LED 290 #define CONFIG_GPIO_LED 291 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 292 #define GREEN_LED_DEV 0 293 #define STATUS_LED_BIT GREEN_LED_GPIO 294 #define STATUS_LED_STATE STATUS_LED_ON 295 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 296 #define STATUS_LED_BOOT GREEN_LED_DEV 297 298 #define CONFIG_SPLASHIMAGE_GUARD 299 300 /* GPIO banks */ 301 #ifdef CONFIG_STATUS_LED 302 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 303 #endif 304 305 /* Display Configuration */ 306 #define CONFIG_OMAP3_GPIO_2 307 #define CONFIG_OMAP3_GPIO_5 308 #define CONFIG_VIDEO_OMAP3 309 #define LCD_BPP LCD_COLOR16 310 311 #define CONFIG_LCD 312 #define CONFIG_SPLASH_SCREEN 313 #define CONFIG_CMD_BMP 314 #define CONFIG_BMP_16BPP 315 #define CONFIG_SCF0403_LCD 316 317 #define CONFIG_OMAP3_SPI 318 319 /* Defines for SPL */ 320 #define CONFIG_SPL_FRAMEWORK 321 #define CONFIG_SPL_NAND_SIMPLE 322 323 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 324 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 325 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 326 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 327 328 #define CONFIG_SPL_BOARD_INIT 329 #define CONFIG_SPL_LIBCOMMON_SUPPORT 330 #define CONFIG_SPL_LIBDISK_SUPPORT 331 #define CONFIG_SPL_I2C_SUPPORT 332 #define CONFIG_SPL_LIBGENERIC_SUPPORT 333 #define CONFIG_SPL_MMC_SUPPORT 334 #define CONFIG_SPL_FAT_SUPPORT 335 #define CONFIG_SPL_SERIAL_SUPPORT 336 #define CONFIG_SPL_NAND_SUPPORT 337 #define CONFIG_SPL_NAND_BASE 338 #define CONFIG_SPL_NAND_DRIVERS 339 #define CONFIG_SPL_NAND_ECC 340 #define CONFIG_SPL_GPIO_SUPPORT 341 #define CONFIG_SPL_POWER_SUPPORT 342 #define CONFIG_SPL_OMAP3_ID_NAND 343 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 344 345 /* NAND boot config */ 346 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 347 #define CONFIG_SYS_NAND_PAGE_COUNT 64 348 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 349 #define CONFIG_SYS_NAND_OOBSIZE 64 350 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 351 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 352 /* 353 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 354 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 355 */ 356 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 357 10, 11, 12 } 358 #define CONFIG_SYS_NAND_ECCSIZE 512 359 #define CONFIG_SYS_NAND_ECCBYTES 3 360 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 361 362 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 363 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 364 365 #define CONFIG_SPL_TEXT_BASE 0x40200800 366 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 367 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 368 369 /* 370 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 371 * older x-loader implementations. And move the BSS area so that it 372 * doesn't overlap with TEXT_BASE. 373 */ 374 #define CONFIG_SYS_TEXT_BASE 0x80008000 375 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 376 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 377 378 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 379 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 380 381 #endif /* __CONFIG_H */ 382