1 /* 2 * (C) Copyright 2011 CompuLab, Ltd. 3 * Mike Rapoport <mike@compulab.co.il> 4 * Igor Grinberg <grinberg@compulab.co.il> 5 * 6 * Based on omap3_beagle.h 7 * (C) Copyright 2006-2008 8 * Texas Instruments. 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Syed Mohammed Khasim <x0khasim@ti.com> 11 * 12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_OMAP /* in a TI OMAP core */ 24 #define CONFIG_OMAP_GPIO 25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 26 #define CONFIG_OMAP_COMMON 27 /* Common ARM Erratas */ 28 #define CONFIG_ARM_ERRATA_454179 29 #define CONFIG_ARM_ERRATA_430973 30 #define CONFIG_ARM_ERRATA_621766 31 32 #define CONFIG_SDRC /* The chip has SDRC controller */ 33 34 #include <asm/arch/cpu.h> /* get chip and board defs */ 35 #include <asm/arch/omap.h> 36 37 /* 38 * Display CPU and Board information 39 */ 40 #define CONFIG_DISPLAY_CPUINFO 41 #define CONFIG_DISPLAY_BOARDINFO 42 43 /* Clock Defines */ 44 #define V_OSCK 26000000 /* Clock output from T2 */ 45 #define V_SCLK (V_OSCK >> 1) 46 47 #define CONFIG_MISC_INIT_R 48 49 #define CONFIG_OF_LIBFDT 1 50 51 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 52 #define CONFIG_SETUP_MEMORY_TAGS 53 #define CONFIG_INITRD_TAG 54 #define CONFIG_REVISION_TAG 55 #define CONFIG_SERIAL_TAG 56 57 /* 58 * Size of malloc() pool 59 */ 60 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 61 /* Sector */ 62 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 63 64 /* 65 * Hardware drivers 66 */ 67 68 /* 69 * NS16550 Configuration 70 */ 71 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73 #define CONFIG_SYS_NS16550_SERIAL 74 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 75 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 76 77 /* 78 * select serial console configuration 79 */ 80 #define CONFIG_CONS_INDEX 3 81 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 82 #define CONFIG_SERIAL3 3 /* UART3 */ 83 84 /* allow to overwrite serial and ethaddr */ 85 #define CONFIG_ENV_OVERWRITE 86 #define CONFIG_BAUDRATE 115200 87 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 88 115200} 89 90 #define CONFIG_GENERIC_MMC 91 #define CONFIG_MMC 92 #define CONFIG_OMAP_HSMMC 93 #define CONFIG_DOS_PARTITION 94 95 /* USB */ 96 #define CONFIG_USB_OMAP3 97 #define CONFIG_USB_EHCI 98 #define CONFIG_USB_EHCI_OMAP 99 #define CONFIG_USB_STORAGE 100 #define CONFIG_USB_MUSB_UDC 101 #define CONFIG_TWL4030_USB 102 #define CONFIG_CMD_USB 103 104 /* USB device configuration */ 105 #define CONFIG_USB_DEVICE 106 #define CONFIG_USB_TTY 107 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 108 109 /* commands to include */ 110 #define CONFIG_CMD_CACHE 111 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 112 #define CONFIG_CMD_FAT /* FAT support */ 113 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 114 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 115 #define CONFIG_MTD_PARTITIONS 116 #define MTDIDS_DEFAULT "nand0=nand" 117 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 118 "1920k(u-boot),256k(u-boot-env),"\ 119 "4m(kernel),-(fs)" 120 121 #define CONFIG_CMD_I2C /* I2C serial bus support */ 122 #define CONFIG_CMD_MMC /* MMC support */ 123 #define CONFIG_CMD_NAND /* NAND support */ 124 #define CONFIG_CMD_DHCP 125 #define CONFIG_CMD_PING 126 127 128 #define CONFIG_SYS_NO_FLASH 129 #define CONFIG_SYS_I2C 130 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 131 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 132 #define CONFIG_SYS_I2C_OMAP34XX 133 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 134 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 135 #define CONFIG_SYS_I2C_EEPROM_BUS 0 136 #define CONFIG_I2C_MULTI_BUS 137 138 /* 139 * TWL4030 140 */ 141 #define CONFIG_TWL4030_POWER 142 #define CONFIG_TWL4030_LED 143 144 /* 145 * Board NAND Info. 146 */ 147 #define CONFIG_NAND_OMAP_GPMC 148 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 149 /* to access nand */ 150 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 151 /* to access nand at */ 152 /* CS0 */ 153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 154 /* devices */ 155 156 /* Environment information */ 157 #define CONFIG_BOOTDELAY 3 158 #define CONFIG_ZERO_BOOTDELAY_CHECK 159 160 #define CONFIG_EXTRA_ENV_SETTINGS \ 161 "loadaddr=0x82000000\0" \ 162 "usbtty=cdc_acm\0" \ 163 "console=ttyO2,115200n8\0" \ 164 "mpurate=500\0" \ 165 "vram=12M\0" \ 166 "dvimode=1024x768MR-16@60\0" \ 167 "defaultdisplay=dvi\0" \ 168 "mmcdev=0\0" \ 169 "mmcroot=/dev/mmcblk0p2 rw\0" \ 170 "mmcrootfstype=ext4 rootwait\0" \ 171 "nandroot=/dev/mtdblock4 rw\0" \ 172 "nandrootfstype=ubifs\0" \ 173 "mmcargs=setenv bootargs console=${console} " \ 174 "mpurate=${mpurate} " \ 175 "vram=${vram} " \ 176 "omapfb.mode=dvi:${dvimode} " \ 177 "omapdss.def_disp=${defaultdisplay} " \ 178 "root=${mmcroot} " \ 179 "rootfstype=${mmcrootfstype}\0" \ 180 "nandargs=setenv bootargs console=${console} " \ 181 "mpurate=${mpurate} " \ 182 "vram=${vram} " \ 183 "omapfb.mode=dvi:${dvimode} " \ 184 "omapdss.def_disp=${defaultdisplay} " \ 185 "root=${nandroot} " \ 186 "rootfstype=${nandrootfstype}\0" \ 187 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 188 "bootscript=echo Running bootscript from mmc ...; " \ 189 "source ${loadaddr}\0" \ 190 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 191 "mmcboot=echo Booting from mmc ...; " \ 192 "run mmcargs; " \ 193 "bootm ${loadaddr}\0" \ 194 "nandboot=echo Booting from nand ...; " \ 195 "run nandargs; " \ 196 "nand read ${loadaddr} 2a0000 400000; " \ 197 "bootm ${loadaddr}\0" \ 198 199 #define CONFIG_CMD_BOOTZ 200 #define CONFIG_BOOTCOMMAND \ 201 "mmc dev ${mmcdev}; if mmc rescan; then " \ 202 "if run loadbootscript; then " \ 203 "run bootscript; " \ 204 "else " \ 205 "if run loaduimage; then " \ 206 "run mmcboot; " \ 207 "else run nandboot; " \ 208 "fi; " \ 209 "fi; " \ 210 "else run nandboot; fi" 211 212 /* 213 * Miscellaneous configurable options 214 */ 215 #define CONFIG_AUTO_COMPLETE 216 #define CONFIG_CMDLINE_EDITING 217 #define CONFIG_TIMESTAMP 218 #define CONFIG_SYS_AUTOLOAD "no" 219 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 220 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 221 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 222 /* Print Buffer Size */ 223 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 224 sizeof(CONFIG_SYS_PROMPT) + 16) 225 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 226 /* Boot Argument Buffer Size */ 227 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 228 229 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 230 /* works on */ 231 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 232 0x01F00000) /* 31MB */ 233 234 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 235 /* load address */ 236 237 /* 238 * OMAP3 has 12 GP timers, they can be driven by the system clock 239 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 240 * This rate is divided by a local divisor. 241 */ 242 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 243 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 244 245 /*----------------------------------------------------------------------- 246 * Physical Memory Map 247 */ 248 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 249 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 250 251 /*----------------------------------------------------------------------- 252 * FLASH and environment organization 253 */ 254 255 /* **** PISMO SUPPORT *** */ 256 /* Monitor at start of flash */ 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 258 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 259 260 #define CONFIG_ENV_IS_IN_NAND 261 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 262 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 263 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 264 265 #if defined(CONFIG_CMD_NET) 266 #define CONFIG_SMC911X 267 #define CONFIG_SMC911X_32_BIT 268 #define CM_T3X_SMC911X_BASE 0x2C000000 269 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 270 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 271 #endif /* (CONFIG_CMD_NET) */ 272 273 /* additions for new relocation code, must be added to all boards */ 274 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 275 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 276 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 277 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 278 CONFIG_SYS_INIT_RAM_SIZE - \ 279 GENERATED_GBL_DATA_SIZE) 280 281 /* Status LED */ 282 #define CONFIG_STATUS_LED /* Status LED enabled */ 283 #define CONFIG_BOARD_SPECIFIC_LED 284 #define CONFIG_GPIO_LED 285 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 286 #define GREEN_LED_DEV 0 287 #define STATUS_LED_BIT GREEN_LED_GPIO 288 #define STATUS_LED_STATE STATUS_LED_ON 289 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 290 #define STATUS_LED_BOOT GREEN_LED_DEV 291 292 #define CONFIG_SPLASHIMAGE_GUARD 293 294 /* GPIO banks */ 295 #ifdef CONFIG_STATUS_LED 296 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 297 #endif 298 299 /* Display Configuration */ 300 #define CONFIG_OMAP3_GPIO_2 301 #define CONFIG_OMAP3_GPIO_5 302 #define CONFIG_VIDEO_OMAP3 303 #define LCD_BPP LCD_COLOR16 304 305 #define CONFIG_LCD 306 #define CONFIG_SPLASH_SCREEN 307 #define CONFIG_SPLASH_SOURCE 308 #define CONFIG_CMD_BMP 309 #define CONFIG_BMP_16BPP 310 #define CONFIG_SCF0403_LCD 311 312 #define CONFIG_OMAP3_SPI 313 314 /* Defines for SPL */ 315 #define CONFIG_SPL_FRAMEWORK 316 #define CONFIG_SPL_NAND_SIMPLE 317 318 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 319 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 320 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 321 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 322 323 #define CONFIG_SPL_BOARD_INIT 324 #define CONFIG_SPL_LIBCOMMON_SUPPORT 325 #define CONFIG_SPL_LIBDISK_SUPPORT 326 #define CONFIG_SPL_I2C_SUPPORT 327 #define CONFIG_SPL_LIBGENERIC_SUPPORT 328 #define CONFIG_SPL_MMC_SUPPORT 329 #define CONFIG_SPL_FAT_SUPPORT 330 #define CONFIG_SPL_SERIAL_SUPPORT 331 #define CONFIG_SPL_NAND_SUPPORT 332 #define CONFIG_SPL_NAND_BASE 333 #define CONFIG_SPL_NAND_DRIVERS 334 #define CONFIG_SPL_NAND_ECC 335 #define CONFIG_SPL_GPIO_SUPPORT 336 #define CONFIG_SPL_POWER_SUPPORT 337 #define CONFIG_SPL_OMAP3_ID_NAND 338 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 339 340 /* NAND boot config */ 341 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 342 #define CONFIG_SYS_NAND_PAGE_COUNT 64 343 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 344 #define CONFIG_SYS_NAND_OOBSIZE 64 345 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 346 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 347 /* 348 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 349 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 350 */ 351 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 352 10, 11, 12 } 353 #define CONFIG_SYS_NAND_ECCSIZE 512 354 #define CONFIG_SYS_NAND_ECCBYTES 3 355 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 356 357 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 358 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 359 360 #define CONFIG_SPL_TEXT_BASE 0x40200800 361 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 362 363 /* 364 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 365 * older x-loader implementations. And move the BSS area so that it 366 * doesn't overlap with TEXT_BASE. 367 */ 368 #define CONFIG_SYS_TEXT_BASE 0x80008000 369 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 370 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 371 372 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 373 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 374 375 #endif /* __CONFIG_H */ 376