136b4e2ddSMike Rapoport /* 29fc376beSNikita Kiryanov * (C) Copyright 2011 CompuLab, Ltd. 336b4e2ddSMike Rapoport * Mike Rapoport <mike@compulab.co.il> 4dccd9a0bSIgor Grinberg * Igor Grinberg <grinberg@compulab.co.il> 536b4e2ddSMike Rapoport * 636b4e2ddSMike Rapoport * Based on omap3_beagle.h 736b4e2ddSMike Rapoport * (C) Copyright 2006-2008 836b4e2ddSMike Rapoport * Texas Instruments. 936b4e2ddSMike Rapoport * Richard Woodruff <r-woodruff2@ti.com> 1036b4e2ddSMike Rapoport * Syed Mohammed Khasim <x0khasim@ti.com> 1136b4e2ddSMike Rapoport * 12b65a77a8SIgor Grinberg * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 1336b4e2ddSMike Rapoport * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1536b4e2ddSMike Rapoport */ 1636b4e2ddSMike Rapoport 1736b4e2ddSMike Rapoport #ifndef __CONFIG_H 1836b4e2ddSMike Rapoport #define __CONFIG_H 1936b4e2ddSMike Rapoport 203709844fSAlbert ARIBAUD #define CONFIG_SYS_CACHELINE_SIZE 64 213709844fSAlbert ARIBAUD 2236b4e2ddSMike Rapoport /* 2336b4e2ddSMike Rapoport * High Level Configuration Options 2436b4e2ddSMike Rapoport */ 259fc376beSNikita Kiryanov #define CONFIG_OMAP /* in a TI OMAP core */ 26308252adSMarek Vasut #define CONFIG_OMAP_GPIO 279fc376beSNikita Kiryanov #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 28806d2792SLokesh Vutla #define CONFIG_OMAP_COMMON 29c6f90e14SNishanth Menon /* Common ARM Erratas */ 30c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_454179 31c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_430973 32c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_621766 3336b4e2ddSMike Rapoport 3436b4e2ddSMike Rapoport #define CONFIG_SDRC /* The chip has SDRC controller */ 3536b4e2ddSMike Rapoport 3636b4e2ddSMike Rapoport #include <asm/arch/cpu.h> /* get chip and board defs */ 37987ec585SNishanth Menon #include <asm/arch/omap.h> 3836b4e2ddSMike Rapoport 3936b4e2ddSMike Rapoport /* 4036b4e2ddSMike Rapoport * Display CPU and Board information 4136b4e2ddSMike Rapoport */ 429fc376beSNikita Kiryanov #define CONFIG_DISPLAY_CPUINFO 439fc376beSNikita Kiryanov #define CONFIG_DISPLAY_BOARDINFO 4436b4e2ddSMike Rapoport 4536b4e2ddSMike Rapoport /* Clock Defines */ 4636b4e2ddSMike Rapoport #define V_OSCK 26000000 /* Clock output from T2 */ 4736b4e2ddSMike Rapoport #define V_SCLK (V_OSCK >> 1) 4836b4e2ddSMike Rapoport 4936b4e2ddSMike Rapoport #define CONFIG_MISC_INIT_R 5036b4e2ddSMike Rapoport 519fc376beSNikita Kiryanov #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 529fc376beSNikita Kiryanov #define CONFIG_SETUP_MEMORY_TAGS 539fc376beSNikita Kiryanov #define CONFIG_INITRD_TAG 549fc376beSNikita Kiryanov #define CONFIG_REVISION_TAG 5582309250SNikita Kiryanov #define CONFIG_SERIAL_TAG 5636b4e2ddSMike Rapoport 5736b4e2ddSMike Rapoport /* 5836b4e2ddSMike Rapoport * Size of malloc() pool 5936b4e2ddSMike Rapoport */ 60390cdcdaSIgor Grinberg #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 6136b4e2ddSMike Rapoport /* Sector */ 6236b4e2ddSMike Rapoport #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 6336b4e2ddSMike Rapoport 6436b4e2ddSMike Rapoport /* 6536b4e2ddSMike Rapoport * Hardware drivers 6636b4e2ddSMike Rapoport */ 6736b4e2ddSMike Rapoport 6836b4e2ddSMike Rapoport /* 6936b4e2ddSMike Rapoport * NS16550 Configuration 7036b4e2ddSMike Rapoport */ 7136b4e2ddSMike Rapoport #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 7236b4e2ddSMike Rapoport 7336b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_SERIAL 7436b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_REG_SIZE (-4) 7536b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 7636b4e2ddSMike Rapoport 7736b4e2ddSMike Rapoport /* 7836b4e2ddSMike Rapoport * select serial console configuration 7936b4e2ddSMike Rapoport */ 8036b4e2ddSMike Rapoport #define CONFIG_CONS_INDEX 3 8136b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 8236b4e2ddSMike Rapoport #define CONFIG_SERIAL3 3 /* UART3 */ 8336b4e2ddSMike Rapoport 8436b4e2ddSMike Rapoport /* allow to overwrite serial and ethaddr */ 8536b4e2ddSMike Rapoport #define CONFIG_ENV_OVERWRITE 8636b4e2ddSMike Rapoport #define CONFIG_BAUDRATE 115200 8736b4e2ddSMike Rapoport #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 8836b4e2ddSMike Rapoport 115200} 899fc376beSNikita Kiryanov 909fc376beSNikita Kiryanov #define CONFIG_GENERIC_MMC 919fc376beSNikita Kiryanov #define CONFIG_MMC 929fc376beSNikita Kiryanov #define CONFIG_OMAP_HSMMC 939fc376beSNikita Kiryanov #define CONFIG_DOS_PARTITION 9436b4e2ddSMike Rapoport 9536b4e2ddSMike Rapoport /* USB */ 969fc376beSNikita Kiryanov #define CONFIG_USB_OMAP3 97854a7836SNikita Kiryanov #define CONFIG_USB_EHCI 98854a7836SNikita Kiryanov #define CONFIG_USB_EHCI_OMAP 99854a7836SNikita Kiryanov #define CONFIG_USB_STORAGE 10095de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC 1019fc376beSNikita Kiryanov #define CONFIG_TWL4030_USB 10236b4e2ddSMike Rapoport 10336b4e2ddSMike Rapoport /* USB device configuration */ 1049fc376beSNikita Kiryanov #define CONFIG_USB_DEVICE 1059fc376beSNikita Kiryanov #define CONFIG_USB_TTY 1069fc376beSNikita Kiryanov #define CONFIG_SYS_CONSOLE_IS_IN_ENV 10736b4e2ddSMike Rapoport 10836b4e2ddSMike Rapoport /* commands to include */ 10936b4e2ddSMike Rapoport #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 11036b4e2ddSMike Rapoport #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 1110b800a6bSIgor Grinberg #define CONFIG_MTD_PARTITIONS 11236b4e2ddSMike Rapoport #define MTDIDS_DEFAULT "nand0=nand" 11336b4e2ddSMike Rapoport #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 1140b800a6bSIgor Grinberg "1920k(u-boot),256k(u-boot-env),"\ 11536b4e2ddSMike Rapoport "4m(kernel),-(fs)" 11636b4e2ddSMike Rapoport 11736b4e2ddSMike Rapoport #define CONFIG_CMD_NAND /* NAND support */ 11836b4e2ddSMike Rapoport 11936b4e2ddSMike Rapoport #define CONFIG_SYS_NO_FLASH 1206789e84eSHeiko Schocher #define CONFIG_SYS_I2C 1216789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 1226789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 1236789e84eSHeiko Schocher #define CONFIG_SYS_I2C_OMAP34XX 12482309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 12582309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 12652658fdaSNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_BUS 0 12779874ae9SNikita Kiryanov #define CONFIG_I2C_MULTI_BUS 12836b4e2ddSMike Rapoport 12936b4e2ddSMike Rapoport /* 13036b4e2ddSMike Rapoport * TWL4030 13136b4e2ddSMike Rapoport */ 1329fc376beSNikita Kiryanov #define CONFIG_TWL4030_POWER 1339fc376beSNikita Kiryanov #define CONFIG_TWL4030_LED 13436b4e2ddSMike Rapoport 13536b4e2ddSMike Rapoport /* 13636b4e2ddSMike Rapoport * Board NAND Info. 13736b4e2ddSMike Rapoport */ 13836b4e2ddSMike Rapoport #define CONFIG_NAND_OMAP_GPMC 13936b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 14036b4e2ddSMike Rapoport /* to access nand */ 14136b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 14236b4e2ddSMike Rapoport /* to access nand at */ 14336b4e2ddSMike Rapoport /* CS0 */ 14436b4e2ddSMike Rapoport #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 14536b4e2ddSMike Rapoport /* devices */ 1467bb6e29bSStefan Roese 14736b4e2ddSMike Rapoport /* Environment information */ 148a431be4cSNikita Kiryanov #define CONFIG_BOOTDELAY 3 1499bd5c1adSNikita Kiryanov #define CONFIG_ZERO_BOOTDELAY_CHECK 15036b4e2ddSMike Rapoport 15136b4e2ddSMike Rapoport #define CONFIG_EXTRA_ENV_SETTINGS \ 15236b4e2ddSMike Rapoport "loadaddr=0x82000000\0" \ 15336b4e2ddSMike Rapoport "usbtty=cdc_acm\0" \ 154f3ef3609SNikita Kiryanov "console=ttyO2,115200n8\0" \ 15536b4e2ddSMike Rapoport "mpurate=500\0" \ 15636b4e2ddSMike Rapoport "vram=12M\0" \ 15736b4e2ddSMike Rapoport "dvimode=1024x768MR-16@60\0" \ 15836b4e2ddSMike Rapoport "defaultdisplay=dvi\0" \ 15936b4e2ddSMike Rapoport "mmcdev=0\0" \ 16036b4e2ddSMike Rapoport "mmcroot=/dev/mmcblk0p2 rw\0" \ 1610b800a6bSIgor Grinberg "mmcrootfstype=ext4 rootwait\0" \ 16236b4e2ddSMike Rapoport "nandroot=/dev/mtdblock4 rw\0" \ 1630b800a6bSIgor Grinberg "nandrootfstype=ubifs\0" \ 16436b4e2ddSMike Rapoport "mmcargs=setenv bootargs console=${console} " \ 16536b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 16636b4e2ddSMike Rapoport "vram=${vram} " \ 16736b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 16836b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 16936b4e2ddSMike Rapoport "root=${mmcroot} " \ 17036b4e2ddSMike Rapoport "rootfstype=${mmcrootfstype}\0" \ 17136b4e2ddSMike Rapoport "nandargs=setenv bootargs console=${console} " \ 17236b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 17336b4e2ddSMike Rapoport "vram=${vram} " \ 17436b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 17536b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 17636b4e2ddSMike Rapoport "root=${nandroot} " \ 17736b4e2ddSMike Rapoport "rootfstype=${nandrootfstype}\0" \ 17836b4e2ddSMike Rapoport "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 17936b4e2ddSMike Rapoport "bootscript=echo Running bootscript from mmc ...; " \ 18036b4e2ddSMike Rapoport "source ${loadaddr}\0" \ 18136b4e2ddSMike Rapoport "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 18236b4e2ddSMike Rapoport "mmcboot=echo Booting from mmc ...; " \ 18336b4e2ddSMike Rapoport "run mmcargs; " \ 18436b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 18536b4e2ddSMike Rapoport "nandboot=echo Booting from nand ...; " \ 18636b4e2ddSMike Rapoport "run nandargs; " \ 1870b800a6bSIgor Grinberg "nand read ${loadaddr} 2a0000 400000; " \ 18836b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 18936b4e2ddSMike Rapoport 19036b4e2ddSMike Rapoport #define CONFIG_BOOTCOMMAND \ 19166968110SAndrew Bradford "mmc dev ${mmcdev}; if mmc rescan; then " \ 19236b4e2ddSMike Rapoport "if run loadbootscript; then " \ 19336b4e2ddSMike Rapoport "run bootscript; " \ 19436b4e2ddSMike Rapoport "else " \ 19536b4e2ddSMike Rapoport "if run loaduimage; then " \ 19636b4e2ddSMike Rapoport "run mmcboot; " \ 19736b4e2ddSMike Rapoport "else run nandboot; " \ 19836b4e2ddSMike Rapoport "fi; " \ 19936b4e2ddSMike Rapoport "fi; " \ 20036b4e2ddSMike Rapoport "else run nandboot; fi" 20136b4e2ddSMike Rapoport 20236b4e2ddSMike Rapoport /* 20336b4e2ddSMike Rapoport * Miscellaneous configurable options 20436b4e2ddSMike Rapoport */ 20541d7e702SIgor Grinberg #define CONFIG_AUTO_COMPLETE 20641d7e702SIgor Grinberg #define CONFIG_CMDLINE_EDITING 20741d7e702SIgor Grinberg #define CONFIG_TIMESTAMP 20841d7e702SIgor Grinberg #define CONFIG_SYS_AUTOLOAD "no" 20936b4e2ddSMike Rapoport #define CONFIG_SYS_LONGHELP /* undef to save memory */ 21036b4e2ddSMike Rapoport #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 21136b4e2ddSMike Rapoport /* Print Buffer Size */ 21236b4e2ddSMike Rapoport #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 21336b4e2ddSMike Rapoport sizeof(CONFIG_SYS_PROMPT) + 16) 21436b4e2ddSMike Rapoport #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 21536b4e2ddSMike Rapoport /* Boot Argument Buffer Size */ 21636b4e2ddSMike Rapoport #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 21736b4e2ddSMike Rapoport 21836b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 21936b4e2ddSMike Rapoport /* works on */ 22036b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 22136b4e2ddSMike Rapoport 0x01F00000) /* 31MB */ 22236b4e2ddSMike Rapoport 22336b4e2ddSMike Rapoport #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 22436b4e2ddSMike Rapoport /* load address */ 22536b4e2ddSMike Rapoport 22636b4e2ddSMike Rapoport /* 22736b4e2ddSMike Rapoport * OMAP3 has 12 GP timers, they can be driven by the system clock 22836b4e2ddSMike Rapoport * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 22936b4e2ddSMike Rapoport * This rate is divided by a local divisor. 23036b4e2ddSMike Rapoport */ 23136b4e2ddSMike Rapoport #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 23236b4e2ddSMike Rapoport #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 23336b4e2ddSMike Rapoport 23436b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 23536b4e2ddSMike Rapoport * Physical Memory Map 23636b4e2ddSMike Rapoport */ 23736b4e2ddSMike Rapoport #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 23836b4e2ddSMike Rapoport #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 23936b4e2ddSMike Rapoport 24036b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 24136b4e2ddSMike Rapoport * FLASH and environment organization 24236b4e2ddSMike Rapoport */ 24336b4e2ddSMike Rapoport 24436b4e2ddSMike Rapoport /* **** PISMO SUPPORT *** */ 24536b4e2ddSMike Rapoport /* Monitor at start of flash */ 24636b4e2ddSMike Rapoport #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 2473530a35dSIgor Grinberg #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 24836b4e2ddSMike Rapoport 2499fc376beSNikita Kiryanov #define CONFIG_ENV_IS_IN_NAND 25036b4e2ddSMike Rapoport #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 2516cbec7b3SLuca Ceresoli #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 25236b4e2ddSMike Rapoport #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 25336b4e2ddSMike Rapoport 25436b4e2ddSMike Rapoport #if defined(CONFIG_CMD_NET) 25536b4e2ddSMike Rapoport #define CONFIG_SMC911X 25636b4e2ddSMike Rapoport #define CONFIG_SMC911X_32_BIT 257b65a77a8SIgor Grinberg #define CM_T3X_SMC911X_BASE 0x2C000000 258b65a77a8SIgor Grinberg #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 259b65a77a8SIgor Grinberg #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 26036b4e2ddSMike Rapoport #endif /* (CONFIG_CMD_NET) */ 26136b4e2ddSMike Rapoport 26236b4e2ddSMike Rapoport /* additions for new relocation code, must be added to all boards */ 26336b4e2ddSMike Rapoport #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 26436b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 26536b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_SIZE 0x800 26636b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 26736b4e2ddSMike Rapoport CONFIG_SYS_INIT_RAM_SIZE - \ 26836b4e2ddSMike Rapoport GENERATED_GBL_DATA_SIZE) 26936b4e2ddSMike Rapoport 2702b8754b2SIgor Grinberg /* Status LED */ 2719fc376beSNikita Kiryanov #define CONFIG_STATUS_LED /* Status LED enabled */ 2729fc376beSNikita Kiryanov #define CONFIG_BOARD_SPECIFIC_LED 273ebc18afdSIgor Grinberg #define CONFIG_GPIO_LED 274ebc18afdSIgor Grinberg #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 275ebc18afdSIgor Grinberg #define GREEN_LED_DEV 0 276ebc18afdSIgor Grinberg #define STATUS_LED_BIT GREEN_LED_GPIO 2772b8754b2SIgor Grinberg #define STATUS_LED_STATE STATUS_LED_ON 2782b8754b2SIgor Grinberg #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 279ebc18afdSIgor Grinberg #define STATUS_LED_BOOT GREEN_LED_DEV 2802b8754b2SIgor Grinberg 28160e6bdccSNikita Kiryanov #define CONFIG_SPLASHIMAGE_GUARD 28260e6bdccSNikita Kiryanov 2832b8754b2SIgor Grinberg /* GPIO banks */ 2842b8754b2SIgor Grinberg #ifdef CONFIG_STATUS_LED 2859fc376beSNikita Kiryanov #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 2862b8754b2SIgor Grinberg #endif 2872b8754b2SIgor Grinberg 2887878ca51SNikita Kiryanov /* Display Configuration */ 2897878ca51SNikita Kiryanov #define CONFIG_OMAP3_GPIO_2 2906f72892aSNikita Kiryanov #define CONFIG_OMAP3_GPIO_5 2917878ca51SNikita Kiryanov #define CONFIG_VIDEO_OMAP3 2927878ca51SNikita Kiryanov #define LCD_BPP LCD_COLOR16 2937878ca51SNikita Kiryanov 2947878ca51SNikita Kiryanov #define CONFIG_LCD 295f35034feSNikita Kiryanov #define CONFIG_SPLASH_SCREEN 296f82eb2faSNikita Kiryanov #define CONFIG_SPLASH_SOURCE 297f35034feSNikita Kiryanov #define CONFIG_CMD_BMP 298f35034feSNikita Kiryanov #define CONFIG_BMP_16BPP 29963c4f17bSNikita Kiryanov #define CONFIG_SCF0403_LCD 30063c4f17bSNikita Kiryanov 30163c4f17bSNikita Kiryanov #define CONFIG_OMAP3_SPI 3027878ca51SNikita Kiryanov 3033e51b7c8SStefan Roese /* Defines for SPL */ 3043e51b7c8SStefan Roese #define CONFIG_SPL_FRAMEWORK 3053e51b7c8SStefan Roese #define CONFIG_SPL_NAND_SIMPLE 3063e51b7c8SStefan Roese 3073e51b7c8SStefan Roese #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 3083e51b7c8SStefan Roese #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 309e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 310205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 3113e51b7c8SStefan Roese 3123e51b7c8SStefan Roese #define CONFIG_SPL_BOARD_INIT 3133e51b7c8SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 3143e51b7c8SStefan Roese #define CONFIG_SPL_LIBDISK_SUPPORT 3153e51b7c8SStefan Roese #define CONFIG_SPL_I2C_SUPPORT 3163e51b7c8SStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 3173e51b7c8SStefan Roese #define CONFIG_SPL_MMC_SUPPORT 3183e51b7c8SStefan Roese #define CONFIG_SPL_FAT_SUPPORT 3193e51b7c8SStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 3203e51b7c8SStefan Roese #define CONFIG_SPL_NAND_SUPPORT 3213e51b7c8SStefan Roese #define CONFIG_SPL_NAND_BASE 3223e51b7c8SStefan Roese #define CONFIG_SPL_NAND_DRIVERS 3233e51b7c8SStefan Roese #define CONFIG_SPL_NAND_ECC 3243e51b7c8SStefan Roese #define CONFIG_SPL_GPIO_SUPPORT 3253e51b7c8SStefan Roese #define CONFIG_SPL_POWER_SUPPORT 3263e51b7c8SStefan Roese #define CONFIG_SPL_OMAP3_ID_NAND 3273e51b7c8SStefan Roese #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 3283e51b7c8SStefan Roese 3293e51b7c8SStefan Roese /* NAND boot config */ 3303e51b7c8SStefan Roese #define CONFIG_SYS_NAND_5_ADDR_CYCLE 3313e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_COUNT 64 3323e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_SIZE 2048 3333e51b7c8SStefan Roese #define CONFIG_SYS_NAND_OOBSIZE 64 3343e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 3353e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 3363e51b7c8SStefan Roese /* 3373e51b7c8SStefan Roese * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 3383e51b7c8SStefan Roese * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 3393e51b7c8SStefan Roese */ 3403e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 3413e51b7c8SStefan Roese 10, 11, 12 } 3423e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCSIZE 512 3433e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCBYTES 3 3443e51b7c8SStefan Roese #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 3453e51b7c8SStefan Roese 3463e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 3473e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 3483e51b7c8SStefan Roese 3493e51b7c8SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40200800 3503e51b7c8SStefan Roese #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 3513e51b7c8SStefan Roese 3523e51b7c8SStefan Roese /* 3533e51b7c8SStefan Roese * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 3543e51b7c8SStefan Roese * older x-loader implementations. And move the BSS area so that it 3553e51b7c8SStefan Roese * doesn't overlap with TEXT_BASE. 3563e51b7c8SStefan Roese */ 3573e51b7c8SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x80008000 3583e51b7c8SStefan Roese #define CONFIG_SPL_BSS_START_ADDR 0x80100000 3593e51b7c8SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 3603e51b7c8SStefan Roese 3613e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 3623e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 3633e51b7c8SStefan Roese 364*bcb447e1SNikita Kiryanov /* EEPROM */ 365*bcb447e1SNikita Kiryanov #define CONFIG_CMD_EEPROM 366*bcb447e1SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 367*bcb447e1SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 368*bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 369*bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 370*bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 371*bcb447e1SNikita Kiryanov 372*bcb447e1SNikita Kiryanov #define CONFIG_CMD_EEPROM_LAYOUT 373*bcb447e1SNikita Kiryanov #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" 374*bcb447e1SNikita Kiryanov 37536b4e2ddSMike Rapoport #endif /* __CONFIG_H */ 376