1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 236b4e2ddSMike Rapoport /* 39fc376beSNikita Kiryanov * (C) Copyright 2011 CompuLab, Ltd. 436b4e2ddSMike Rapoport * Mike Rapoport <mike@compulab.co.il> 5dccd9a0bSIgor Grinberg * Igor Grinberg <grinberg@compulab.co.il> 636b4e2ddSMike Rapoport * 736b4e2ddSMike Rapoport * Based on omap3_beagle.h 836b4e2ddSMike Rapoport * (C) Copyright 2006-2008 936b4e2ddSMike Rapoport * Texas Instruments. 1036b4e2ddSMike Rapoport * Richard Woodruff <r-woodruff2@ti.com> 1136b4e2ddSMike Rapoport * Syed Mohammed Khasim <x0khasim@ti.com> 1236b4e2ddSMike Rapoport * 13b65a77a8SIgor Grinberg * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 1436b4e2ddSMike Rapoport */ 1536b4e2ddSMike Rapoport 1636b4e2ddSMike Rapoport #ifndef __CONFIG_H 1736b4e2ddSMike Rapoport #define __CONFIG_H 1836b4e2ddSMike Rapoport 193709844fSAlbert ARIBAUD #define CONFIG_SYS_CACHELINE_SIZE 64 203709844fSAlbert ARIBAUD 2136b4e2ddSMike Rapoport /* 2236b4e2ddSMike Rapoport * High Level Configuration Options 2336b4e2ddSMike Rapoport */ 249fc376beSNikita Kiryanov #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 2536b4e2ddSMike Rapoport 2636b4e2ddSMike Rapoport #include <asm/arch/cpu.h> /* get chip and board defs */ 27987ec585SNishanth Menon #include <asm/arch/omap.h> 2836b4e2ddSMike Rapoport 2936b4e2ddSMike Rapoport /* Clock Defines */ 3036b4e2ddSMike Rapoport #define V_OSCK 26000000 /* Clock output from T2 */ 3136b4e2ddSMike Rapoport #define V_SCLK (V_OSCK >> 1) 3236b4e2ddSMike Rapoport 3336b4e2ddSMike Rapoport #define CONFIG_MISC_INIT_R 3436b4e2ddSMike Rapoport 359fc376beSNikita Kiryanov #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 369fc376beSNikita Kiryanov #define CONFIG_SETUP_MEMORY_TAGS 379fc376beSNikita Kiryanov #define CONFIG_INITRD_TAG 389fc376beSNikita Kiryanov #define CONFIG_REVISION_TAG 3982309250SNikita Kiryanov #define CONFIG_SERIAL_TAG 4036b4e2ddSMike Rapoport 4136b4e2ddSMike Rapoport /* 4236b4e2ddSMike Rapoport * Size of malloc() pool 4336b4e2ddSMike Rapoport */ 44390cdcdaSIgor Grinberg #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 4536b4e2ddSMike Rapoport /* Sector */ 4636b4e2ddSMike Rapoport #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 4736b4e2ddSMike Rapoport 4836b4e2ddSMike Rapoport /* 4936b4e2ddSMike Rapoport * Hardware drivers 5036b4e2ddSMike Rapoport */ 5136b4e2ddSMike Rapoport 5236b4e2ddSMike Rapoport /* 5336b4e2ddSMike Rapoport * NS16550 Configuration 5436b4e2ddSMike Rapoport */ 5536b4e2ddSMike Rapoport #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 5636b4e2ddSMike Rapoport 5736b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_SERIAL 5836b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_REG_SIZE (-4) 5936b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 6036b4e2ddSMike Rapoport 6136b4e2ddSMike Rapoport /* 6236b4e2ddSMike Rapoport * select serial console configuration 6336b4e2ddSMike Rapoport */ 6436b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 6536b4e2ddSMike Rapoport #define CONFIG_SERIAL3 3 /* UART3 */ 6636b4e2ddSMike Rapoport 6736b4e2ddSMike Rapoport /* allow to overwrite serial and ethaddr */ 6836b4e2ddSMike Rapoport #define CONFIG_ENV_OVERWRITE 6936b4e2ddSMike Rapoport #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 7036b4e2ddSMike Rapoport 115200} 719fc376beSNikita Kiryanov 7236b4e2ddSMike Rapoport /* USB device configuration */ 739fc376beSNikita Kiryanov #define CONFIG_USB_DEVICE 749fc376beSNikita Kiryanov #define CONFIG_USB_TTY 7536b4e2ddSMike Rapoport 7636b4e2ddSMike Rapoport /* commands to include */ 7736b4e2ddSMike Rapoport #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 780b800a6bSIgor Grinberg #define CONFIG_MTD_PARTITIONS 7936b4e2ddSMike Rapoport 806789e84eSHeiko Schocher #define CONFIG_SYS_I2C 8182309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 8282309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 8352658fdaSNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_BUS 0 8479874ae9SNikita Kiryanov #define CONFIG_I2C_MULTI_BUS 8536b4e2ddSMike Rapoport 8636b4e2ddSMike Rapoport /* 8736b4e2ddSMike Rapoport * TWL4030 8836b4e2ddSMike Rapoport */ 899fc376beSNikita Kiryanov #define CONFIG_TWL4030_LED 9036b4e2ddSMike Rapoport 9136b4e2ddSMike Rapoport /* 9236b4e2ddSMike Rapoport * Board NAND Info. 9336b4e2ddSMike Rapoport */ 9436b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 9536b4e2ddSMike Rapoport /* to access nand */ 9636b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 9736b4e2ddSMike Rapoport /* to access nand at */ 9836b4e2ddSMike Rapoport /* CS0 */ 9936b4e2ddSMike Rapoport #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 10036b4e2ddSMike Rapoport /* devices */ 1017bb6e29bSStefan Roese 10236b4e2ddSMike Rapoport /* Environment information */ 10336b4e2ddSMike Rapoport #define CONFIG_EXTRA_ENV_SETTINGS \ 10436b4e2ddSMike Rapoport "loadaddr=0x82000000\0" \ 10536b4e2ddSMike Rapoport "usbtty=cdc_acm\0" \ 106f3ef3609SNikita Kiryanov "console=ttyO2,115200n8\0" \ 10736b4e2ddSMike Rapoport "mpurate=500\0" \ 10836b4e2ddSMike Rapoport "vram=12M\0" \ 10936b4e2ddSMike Rapoport "dvimode=1024x768MR-16@60\0" \ 11036b4e2ddSMike Rapoport "defaultdisplay=dvi\0" \ 11136b4e2ddSMike Rapoport "mmcdev=0\0" \ 11236b4e2ddSMike Rapoport "mmcroot=/dev/mmcblk0p2 rw\0" \ 1130b800a6bSIgor Grinberg "mmcrootfstype=ext4 rootwait\0" \ 11436b4e2ddSMike Rapoport "nandroot=/dev/mtdblock4 rw\0" \ 1150b800a6bSIgor Grinberg "nandrootfstype=ubifs\0" \ 11636b4e2ddSMike Rapoport "mmcargs=setenv bootargs console=${console} " \ 11736b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 11836b4e2ddSMike Rapoport "vram=${vram} " \ 11936b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 12036b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 12136b4e2ddSMike Rapoport "root=${mmcroot} " \ 12236b4e2ddSMike Rapoport "rootfstype=${mmcrootfstype}\0" \ 12336b4e2ddSMike Rapoport "nandargs=setenv bootargs console=${console} " \ 12436b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 12536b4e2ddSMike Rapoport "vram=${vram} " \ 12636b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 12736b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 12836b4e2ddSMike Rapoport "root=${nandroot} " \ 12936b4e2ddSMike Rapoport "rootfstype=${nandrootfstype}\0" \ 13036b4e2ddSMike Rapoport "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 13136b4e2ddSMike Rapoport "bootscript=echo Running bootscript from mmc ...; " \ 13236b4e2ddSMike Rapoport "source ${loadaddr}\0" \ 13336b4e2ddSMike Rapoport "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 13436b4e2ddSMike Rapoport "mmcboot=echo Booting from mmc ...; " \ 13536b4e2ddSMike Rapoport "run mmcargs; " \ 13636b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 13736b4e2ddSMike Rapoport "nandboot=echo Booting from nand ...; " \ 13836b4e2ddSMike Rapoport "run nandargs; " \ 1390b800a6bSIgor Grinberg "nand read ${loadaddr} 2a0000 400000; " \ 14036b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 14136b4e2ddSMike Rapoport 14236b4e2ddSMike Rapoport #define CONFIG_BOOTCOMMAND \ 14366968110SAndrew Bradford "mmc dev ${mmcdev}; if mmc rescan; then " \ 14436b4e2ddSMike Rapoport "if run loadbootscript; then " \ 14536b4e2ddSMike Rapoport "run bootscript; " \ 14636b4e2ddSMike Rapoport "else " \ 14736b4e2ddSMike Rapoport "if run loaduimage; then " \ 14836b4e2ddSMike Rapoport "run mmcboot; " \ 14936b4e2ddSMike Rapoport "else run nandboot; " \ 15036b4e2ddSMike Rapoport "fi; " \ 15136b4e2ddSMike Rapoport "fi; " \ 15236b4e2ddSMike Rapoport "else run nandboot; fi" 15336b4e2ddSMike Rapoport 15436b4e2ddSMike Rapoport /* 15536b4e2ddSMike Rapoport * Miscellaneous configurable options 15636b4e2ddSMike Rapoport */ 15741d7e702SIgor Grinberg #define CONFIG_TIMESTAMP 15841d7e702SIgor Grinberg #define CONFIG_SYS_AUTOLOAD "no" 15936b4e2ddSMike Rapoport 16036b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 16136b4e2ddSMike Rapoport /* works on */ 16236b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 16336b4e2ddSMike Rapoport 0x01F00000) /* 31MB */ 16436b4e2ddSMike Rapoport 16536b4e2ddSMike Rapoport #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 16636b4e2ddSMike Rapoport /* load address */ 16736b4e2ddSMike Rapoport 16836b4e2ddSMike Rapoport /* 16936b4e2ddSMike Rapoport * OMAP3 has 12 GP timers, they can be driven by the system clock 17036b4e2ddSMike Rapoport * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 17136b4e2ddSMike Rapoport * This rate is divided by a local divisor. 17236b4e2ddSMike Rapoport */ 17336b4e2ddSMike Rapoport #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 17436b4e2ddSMike Rapoport #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 17536b4e2ddSMike Rapoport 17636b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 17736b4e2ddSMike Rapoport * Physical Memory Map 17836b4e2ddSMike Rapoport */ 17936b4e2ddSMike Rapoport #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 18036b4e2ddSMike Rapoport #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 18136b4e2ddSMike Rapoport 18236b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 18336b4e2ddSMike Rapoport * FLASH and environment organization 18436b4e2ddSMike Rapoport */ 18536b4e2ddSMike Rapoport 18636b4e2ddSMike Rapoport /* **** PISMO SUPPORT *** */ 18736b4e2ddSMike Rapoport /* Monitor at start of flash */ 18836b4e2ddSMike Rapoport #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 1893530a35dSIgor Grinberg #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 19036b4e2ddSMike Rapoport 1917672d9d5SAdam Ford #define CONFIG_ENV_OFFSET 0x260000 1927672d9d5SAdam Ford #define CONFIG_ENV_ADDR 0x260000 19336b4e2ddSMike Rapoport 19436b4e2ddSMike Rapoport /* additions for new relocation code, must be added to all boards */ 19536b4e2ddSMike Rapoport #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 19636b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 19736b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_SIZE 0x800 19836b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 19936b4e2ddSMike Rapoport CONFIG_SYS_INIT_RAM_SIZE - \ 20036b4e2ddSMike Rapoport GENERATED_GBL_DATA_SIZE) 20136b4e2ddSMike Rapoport 2022b8754b2SIgor Grinberg /* Status LED */ 203ebc18afdSIgor Grinberg #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 2042b8754b2SIgor Grinberg 20560e6bdccSNikita Kiryanov #define CONFIG_SPLASHIMAGE_GUARD 20660e6bdccSNikita Kiryanov 2077878ca51SNikita Kiryanov /* Display Configuration */ 2087878ca51SNikita Kiryanov #define CONFIG_VIDEO_OMAP3 2097878ca51SNikita Kiryanov #define LCD_BPP LCD_COLOR16 2107878ca51SNikita Kiryanov 211f35034feSNikita Kiryanov #define CONFIG_SPLASH_SCREEN 212f82eb2faSNikita Kiryanov #define CONFIG_SPLASH_SOURCE 213f35034feSNikita Kiryanov #define CONFIG_BMP_16BPP 21463c4f17bSNikita Kiryanov #define CONFIG_SCF0403_LCD 21563c4f17bSNikita Kiryanov 2163e51b7c8SStefan Roese /* Defines for SPL */ 2173e51b7c8SStefan Roese 218e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 219205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 2203e51b7c8SStefan Roese 2213e51b7c8SStefan Roese #define CONFIG_SPL_NAND_BASE 2223e51b7c8SStefan Roese #define CONFIG_SPL_NAND_DRIVERS 2233e51b7c8SStefan Roese #define CONFIG_SPL_NAND_ECC 2243e51b7c8SStefan Roese 2253e51b7c8SStefan Roese /* NAND boot config */ 2263e51b7c8SStefan Roese #define CONFIG_SYS_NAND_5_ADDR_CYCLE 2273e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_COUNT 64 2283e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_SIZE 2048 2293e51b7c8SStefan Roese #define CONFIG_SYS_NAND_OOBSIZE 64 2303e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 2313e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 2323e51b7c8SStefan Roese /* 2333e51b7c8SStefan Roese * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 2343e51b7c8SStefan Roese * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 2353e51b7c8SStefan Roese */ 2363e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 2373e51b7c8SStefan Roese 10, 11, 12 } 2383e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCSIZE 512 2393e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCBYTES 3 2403e51b7c8SStefan Roese #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 2413e51b7c8SStefan Roese 2423e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 2433e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 2443e51b7c8SStefan Roese 2453e51b7c8SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40200800 246fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 247fa2f81b0STom Rini CONFIG_SPL_TEXT_BASE) 2483e51b7c8SStefan Roese 2493e51b7c8SStefan Roese /* 2503e51b7c8SStefan Roese * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 2513e51b7c8SStefan Roese * older x-loader implementations. And move the BSS area so that it 2523e51b7c8SStefan Roese * doesn't overlap with TEXT_BASE. 2533e51b7c8SStefan Roese */ 2543e51b7c8SStefan Roese #define CONFIG_SPL_BSS_START_ADDR 0x80100000 2553e51b7c8SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 2563e51b7c8SStefan Roese 2573e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 2583e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 2593e51b7c8SStefan Roese 260bcb447e1SNikita Kiryanov /* EEPROM */ 261bcb447e1SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 262bcb447e1SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 263bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 264bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 265bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 266bcb447e1SNikita Kiryanov 26736b4e2ddSMike Rapoport #endif /* __CONFIG_H */ 268