136b4e2ddSMike Rapoport /* 29fc376beSNikita Kiryanov * (C) Copyright 2011 CompuLab, Ltd. 336b4e2ddSMike Rapoport * Mike Rapoport <mike@compulab.co.il> 4dccd9a0bSIgor Grinberg * Igor Grinberg <grinberg@compulab.co.il> 536b4e2ddSMike Rapoport * 636b4e2ddSMike Rapoport * Based on omap3_beagle.h 736b4e2ddSMike Rapoport * (C) Copyright 2006-2008 836b4e2ddSMike Rapoport * Texas Instruments. 936b4e2ddSMike Rapoport * Richard Woodruff <r-woodruff2@ti.com> 1036b4e2ddSMike Rapoport * Syed Mohammed Khasim <x0khasim@ti.com> 1136b4e2ddSMike Rapoport * 12b65a77a8SIgor Grinberg * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards 1336b4e2ddSMike Rapoport * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1536b4e2ddSMike Rapoport */ 1636b4e2ddSMike Rapoport 1736b4e2ddSMike Rapoport #ifndef __CONFIG_H 1836b4e2ddSMike Rapoport #define __CONFIG_H 1936b4e2ddSMike Rapoport 203709844fSAlbert ARIBAUD #define CONFIG_SYS_CACHELINE_SIZE 64 213709844fSAlbert ARIBAUD 2236b4e2ddSMike Rapoport /* 2336b4e2ddSMike Rapoport * High Level Configuration Options 2436b4e2ddSMike Rapoport */ 259fc376beSNikita Kiryanov #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ 2636b4e2ddSMike Rapoport 2736b4e2ddSMike Rapoport #define CONFIG_SDRC /* The chip has SDRC controller */ 2836b4e2ddSMike Rapoport 2936b4e2ddSMike Rapoport #include <asm/arch/cpu.h> /* get chip and board defs */ 30987ec585SNishanth Menon #include <asm/arch/omap.h> 3136b4e2ddSMike Rapoport 3236b4e2ddSMike Rapoport /* Clock Defines */ 3336b4e2ddSMike Rapoport #define V_OSCK 26000000 /* Clock output from T2 */ 3436b4e2ddSMike Rapoport #define V_SCLK (V_OSCK >> 1) 3536b4e2ddSMike Rapoport 3636b4e2ddSMike Rapoport #define CONFIG_MISC_INIT_R 3736b4e2ddSMike Rapoport 389fc376beSNikita Kiryanov #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 399fc376beSNikita Kiryanov #define CONFIG_SETUP_MEMORY_TAGS 409fc376beSNikita Kiryanov #define CONFIG_INITRD_TAG 419fc376beSNikita Kiryanov #define CONFIG_REVISION_TAG 4282309250SNikita Kiryanov #define CONFIG_SERIAL_TAG 4336b4e2ddSMike Rapoport 4436b4e2ddSMike Rapoport /* 4536b4e2ddSMike Rapoport * Size of malloc() pool 4636b4e2ddSMike Rapoport */ 47390cdcdaSIgor Grinberg #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 4836b4e2ddSMike Rapoport /* Sector */ 4936b4e2ddSMike Rapoport #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 5036b4e2ddSMike Rapoport 5136b4e2ddSMike Rapoport /* 5236b4e2ddSMike Rapoport * Hardware drivers 5336b4e2ddSMike Rapoport */ 5436b4e2ddSMike Rapoport 5536b4e2ddSMike Rapoport /* 5636b4e2ddSMike Rapoport * NS16550 Configuration 5736b4e2ddSMike Rapoport */ 5836b4e2ddSMike Rapoport #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 5936b4e2ddSMike Rapoport 6036b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_SERIAL 6136b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_REG_SIZE (-4) 6236b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 6336b4e2ddSMike Rapoport 6436b4e2ddSMike Rapoport /* 6536b4e2ddSMike Rapoport * select serial console configuration 6636b4e2ddSMike Rapoport */ 6736b4e2ddSMike Rapoport #define CONFIG_CONS_INDEX 3 6836b4e2ddSMike Rapoport #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 6936b4e2ddSMike Rapoport #define CONFIG_SERIAL3 3 /* UART3 */ 7036b4e2ddSMike Rapoport 7136b4e2ddSMike Rapoport /* allow to overwrite serial and ethaddr */ 7236b4e2ddSMike Rapoport #define CONFIG_ENV_OVERWRITE 7336b4e2ddSMike Rapoport #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 7436b4e2ddSMike Rapoport 115200} 759fc376beSNikita Kiryanov 7636b4e2ddSMike Rapoport /* USB */ 779fc376beSNikita Kiryanov #define CONFIG_USB_OMAP3 7895de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC 799fc376beSNikita Kiryanov #define CONFIG_TWL4030_USB 8036b4e2ddSMike Rapoport 8136b4e2ddSMike Rapoport /* USB device configuration */ 829fc376beSNikita Kiryanov #define CONFIG_USB_DEVICE 839fc376beSNikita Kiryanov #define CONFIG_USB_TTY 8436b4e2ddSMike Rapoport 8536b4e2ddSMike Rapoport /* commands to include */ 8636b4e2ddSMike Rapoport #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 870b800a6bSIgor Grinberg #define CONFIG_MTD_PARTITIONS 8836b4e2ddSMike Rapoport #define MTDIDS_DEFAULT "nand0=nand" 8936b4e2ddSMike Rapoport #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 900b800a6bSIgor Grinberg "1920k(u-boot),256k(u-boot-env),"\ 9136b4e2ddSMike Rapoport "4m(kernel),-(fs)" 9236b4e2ddSMike Rapoport 936789e84eSHeiko Schocher #define CONFIG_SYS_I2C 946789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 956789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 9682309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 9782309250SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 9852658fdaSNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_BUS 0 9979874ae9SNikita Kiryanov #define CONFIG_I2C_MULTI_BUS 10036b4e2ddSMike Rapoport 10136b4e2ddSMike Rapoport /* 10236b4e2ddSMike Rapoport * TWL4030 10336b4e2ddSMike Rapoport */ 1049fc376beSNikita Kiryanov #define CONFIG_TWL4030_LED 10536b4e2ddSMike Rapoport 10636b4e2ddSMike Rapoport /* 10736b4e2ddSMike Rapoport * Board NAND Info. 10836b4e2ddSMike Rapoport */ 10936b4e2ddSMike Rapoport #define CONFIG_NAND_OMAP_GPMC 11036b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 11136b4e2ddSMike Rapoport /* to access nand */ 11236b4e2ddSMike Rapoport #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 11336b4e2ddSMike Rapoport /* to access nand at */ 11436b4e2ddSMike Rapoport /* CS0 */ 11536b4e2ddSMike Rapoport #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 11636b4e2ddSMike Rapoport /* devices */ 1177bb6e29bSStefan Roese 11836b4e2ddSMike Rapoport /* Environment information */ 11936b4e2ddSMike Rapoport #define CONFIG_EXTRA_ENV_SETTINGS \ 12036b4e2ddSMike Rapoport "loadaddr=0x82000000\0" \ 12136b4e2ddSMike Rapoport "usbtty=cdc_acm\0" \ 122f3ef3609SNikita Kiryanov "console=ttyO2,115200n8\0" \ 12336b4e2ddSMike Rapoport "mpurate=500\0" \ 12436b4e2ddSMike Rapoport "vram=12M\0" \ 12536b4e2ddSMike Rapoport "dvimode=1024x768MR-16@60\0" \ 12636b4e2ddSMike Rapoport "defaultdisplay=dvi\0" \ 12736b4e2ddSMike Rapoport "mmcdev=0\0" \ 12836b4e2ddSMike Rapoport "mmcroot=/dev/mmcblk0p2 rw\0" \ 1290b800a6bSIgor Grinberg "mmcrootfstype=ext4 rootwait\0" \ 13036b4e2ddSMike Rapoport "nandroot=/dev/mtdblock4 rw\0" \ 1310b800a6bSIgor Grinberg "nandrootfstype=ubifs\0" \ 13236b4e2ddSMike Rapoport "mmcargs=setenv bootargs console=${console} " \ 13336b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 13436b4e2ddSMike Rapoport "vram=${vram} " \ 13536b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 13636b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 13736b4e2ddSMike Rapoport "root=${mmcroot} " \ 13836b4e2ddSMike Rapoport "rootfstype=${mmcrootfstype}\0" \ 13936b4e2ddSMike Rapoport "nandargs=setenv bootargs console=${console} " \ 14036b4e2ddSMike Rapoport "mpurate=${mpurate} " \ 14136b4e2ddSMike Rapoport "vram=${vram} " \ 14236b4e2ddSMike Rapoport "omapfb.mode=dvi:${dvimode} " \ 14336b4e2ddSMike Rapoport "omapdss.def_disp=${defaultdisplay} " \ 14436b4e2ddSMike Rapoport "root=${nandroot} " \ 14536b4e2ddSMike Rapoport "rootfstype=${nandrootfstype}\0" \ 14636b4e2ddSMike Rapoport "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 14736b4e2ddSMike Rapoport "bootscript=echo Running bootscript from mmc ...; " \ 14836b4e2ddSMike Rapoport "source ${loadaddr}\0" \ 14936b4e2ddSMike Rapoport "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 15036b4e2ddSMike Rapoport "mmcboot=echo Booting from mmc ...; " \ 15136b4e2ddSMike Rapoport "run mmcargs; " \ 15236b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 15336b4e2ddSMike Rapoport "nandboot=echo Booting from nand ...; " \ 15436b4e2ddSMike Rapoport "run nandargs; " \ 1550b800a6bSIgor Grinberg "nand read ${loadaddr} 2a0000 400000; " \ 15636b4e2ddSMike Rapoport "bootm ${loadaddr}\0" \ 15736b4e2ddSMike Rapoport 15836b4e2ddSMike Rapoport #define CONFIG_BOOTCOMMAND \ 15966968110SAndrew Bradford "mmc dev ${mmcdev}; if mmc rescan; then " \ 16036b4e2ddSMike Rapoport "if run loadbootscript; then " \ 16136b4e2ddSMike Rapoport "run bootscript; " \ 16236b4e2ddSMike Rapoport "else " \ 16336b4e2ddSMike Rapoport "if run loaduimage; then " \ 16436b4e2ddSMike Rapoport "run mmcboot; " \ 16536b4e2ddSMike Rapoport "else run nandboot; " \ 16636b4e2ddSMike Rapoport "fi; " \ 16736b4e2ddSMike Rapoport "fi; " \ 16836b4e2ddSMike Rapoport "else run nandboot; fi" 16936b4e2ddSMike Rapoport 17036b4e2ddSMike Rapoport /* 17136b4e2ddSMike Rapoport * Miscellaneous configurable options 17236b4e2ddSMike Rapoport */ 17341d7e702SIgor Grinberg #define CONFIG_AUTO_COMPLETE 17441d7e702SIgor Grinberg #define CONFIG_CMDLINE_EDITING 17541d7e702SIgor Grinberg #define CONFIG_TIMESTAMP 17641d7e702SIgor Grinberg #define CONFIG_SYS_AUTOLOAD "no" 17736b4e2ddSMike Rapoport #define CONFIG_SYS_LONGHELP /* undef to save memory */ 17836b4e2ddSMike Rapoport 17936b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ 18036b4e2ddSMike Rapoport /* works on */ 18136b4e2ddSMike Rapoport #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 18236b4e2ddSMike Rapoport 0x01F00000) /* 31MB */ 18336b4e2ddSMike Rapoport 18436b4e2ddSMike Rapoport #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 18536b4e2ddSMike Rapoport /* load address */ 18636b4e2ddSMike Rapoport 18736b4e2ddSMike Rapoport /* 18836b4e2ddSMike Rapoport * OMAP3 has 12 GP timers, they can be driven by the system clock 18936b4e2ddSMike Rapoport * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 19036b4e2ddSMike Rapoport * This rate is divided by a local divisor. 19136b4e2ddSMike Rapoport */ 19236b4e2ddSMike Rapoport #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 19336b4e2ddSMike Rapoport #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 19436b4e2ddSMike Rapoport 19536b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 19636b4e2ddSMike Rapoport * Physical Memory Map 19736b4e2ddSMike Rapoport */ 19836b4e2ddSMike Rapoport #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ 19936b4e2ddSMike Rapoport #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 20036b4e2ddSMike Rapoport 20136b4e2ddSMike Rapoport /*----------------------------------------------------------------------- 20236b4e2ddSMike Rapoport * FLASH and environment organization 20336b4e2ddSMike Rapoport */ 20436b4e2ddSMike Rapoport 20536b4e2ddSMike Rapoport /* **** PISMO SUPPORT *** */ 20636b4e2ddSMike Rapoport /* Monitor at start of flash */ 20736b4e2ddSMike Rapoport #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 2083530a35dSIgor Grinberg #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 20936b4e2ddSMike Rapoport 210*7672d9d5SAdam Ford #define CONFIG_ENV_OFFSET 0x260000 211*7672d9d5SAdam Ford #define CONFIG_ENV_ADDR 0x260000 21236b4e2ddSMike Rapoport 21336b4e2ddSMike Rapoport #if defined(CONFIG_CMD_NET) 21436b4e2ddSMike Rapoport #define CONFIG_SMC911X 21536b4e2ddSMike Rapoport #define CONFIG_SMC911X_32_BIT 216b65a77a8SIgor Grinberg #define CM_T3X_SMC911X_BASE 0x2C000000 217b65a77a8SIgor Grinberg #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) 218b65a77a8SIgor Grinberg #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE 21936b4e2ddSMike Rapoport #endif /* (CONFIG_CMD_NET) */ 22036b4e2ddSMike Rapoport 22136b4e2ddSMike Rapoport /* additions for new relocation code, must be added to all boards */ 22236b4e2ddSMike Rapoport #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 22336b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 22436b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_RAM_SIZE 0x800 22536b4e2ddSMike Rapoport #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 22636b4e2ddSMike Rapoport CONFIG_SYS_INIT_RAM_SIZE - \ 22736b4e2ddSMike Rapoport GENERATED_GBL_DATA_SIZE) 22836b4e2ddSMike Rapoport 2292b8754b2SIgor Grinberg /* Status LED */ 230ebc18afdSIgor Grinberg #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ 2312b8754b2SIgor Grinberg 23260e6bdccSNikita Kiryanov #define CONFIG_SPLASHIMAGE_GUARD 23360e6bdccSNikita Kiryanov 2347878ca51SNikita Kiryanov /* Display Configuration */ 2357878ca51SNikita Kiryanov #define CONFIG_VIDEO_OMAP3 2367878ca51SNikita Kiryanov #define LCD_BPP LCD_COLOR16 2377878ca51SNikita Kiryanov 238f35034feSNikita Kiryanov #define CONFIG_SPLASH_SCREEN 239f82eb2faSNikita Kiryanov #define CONFIG_SPLASH_SOURCE 240f35034feSNikita Kiryanov #define CONFIG_BMP_16BPP 24163c4f17bSNikita Kiryanov #define CONFIG_SCF0403_LCD 24263c4f17bSNikita Kiryanov 2433e51b7c8SStefan Roese /* Defines for SPL */ 2443e51b7c8SStefan Roese #define CONFIG_SPL_FRAMEWORK 2453e51b7c8SStefan Roese #define CONFIG_SPL_NAND_SIMPLE 2463e51b7c8SStefan Roese 247e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 248205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 2493e51b7c8SStefan Roese 2503e51b7c8SStefan Roese #define CONFIG_SPL_NAND_BASE 2513e51b7c8SStefan Roese #define CONFIG_SPL_NAND_DRIVERS 2523e51b7c8SStefan Roese #define CONFIG_SPL_NAND_ECC 2533e51b7c8SStefan Roese 2543e51b7c8SStefan Roese /* NAND boot config */ 2553e51b7c8SStefan Roese #define CONFIG_SYS_NAND_5_ADDR_CYCLE 2563e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_COUNT 64 2573e51b7c8SStefan Roese #define CONFIG_SYS_NAND_PAGE_SIZE 2048 2583e51b7c8SStefan Roese #define CONFIG_SYS_NAND_OOBSIZE 64 2593e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 2603e51b7c8SStefan Roese #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 2613e51b7c8SStefan Roese /* 2623e51b7c8SStefan Roese * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 2633e51b7c8SStefan Roese * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 2643e51b7c8SStefan Roese */ 2653e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ 2663e51b7c8SStefan Roese 10, 11, 12 } 2673e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCSIZE 512 2683e51b7c8SStefan Roese #define CONFIG_SYS_NAND_ECCBYTES 3 2693e51b7c8SStefan Roese #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 2703e51b7c8SStefan Roese 2713e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 2723e51b7c8SStefan Roese #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 2733e51b7c8SStefan Roese 2743e51b7c8SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40200800 275fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 276fa2f81b0STom Rini CONFIG_SPL_TEXT_BASE) 2773e51b7c8SStefan Roese 2783e51b7c8SStefan Roese /* 2793e51b7c8SStefan Roese * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 2803e51b7c8SStefan Roese * older x-loader implementations. And move the BSS area so that it 2813e51b7c8SStefan Roese * doesn't overlap with TEXT_BASE. 2823e51b7c8SStefan Roese */ 2833e51b7c8SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x80008000 2843e51b7c8SStefan Roese #define CONFIG_SPL_BSS_START_ADDR 0x80100000 2853e51b7c8SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 2863e51b7c8SStefan Roese 2873e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 2883e51b7c8SStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 2893e51b7c8SStefan Roese 290bcb447e1SNikita Kiryanov /* EEPROM */ 291bcb447e1SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 292bcb447e1SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 293bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 294bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 295bcb447e1SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 296bcb447e1SNikita Kiryanov 29736b4e2ddSMike Rapoport #endif /* __CONFIG_H */ 298