1 /* 2 * Config file for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_CM_FX6_H 12 #define __CONFIG_CM_FX6_H 13 14 #include "mx6_common.h" 15 16 /* Machine config */ 17 #define CONFIG_SYS_LITTLE_ENDIAN 18 #define CONFIG_MACH_TYPE 4273 19 20 /* CMD */ 21 #define CONFIG_CMD_MTDPARTS 22 23 /* MMC */ 24 #define CONFIG_SYS_FSL_USDHC_NUM 3 25 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR 26 27 /* RAM */ 28 #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR 29 #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR 30 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 31 #define CONFIG_NR_DRAM_BANKS 2 32 #define CONFIG_SYS_MEMTEST_START 0x10000000 33 #define CONFIG_SYS_MEMTEST_END 0x10010000 34 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 36 #define CONFIG_SYS_INIT_SP_OFFSET \ 37 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 38 #define CONFIG_SYS_INIT_SP_ADDR \ 39 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 40 41 /* Serial console */ 42 #define CONFIG_MXC_UART 43 #define CONFIG_MXC_UART_BASE UART4_BASE 44 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 45 46 /* Shell */ 47 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 48 sizeof(CONFIG_SYS_PROMPT) + 16) 49 50 /* SPI flash */ 51 #define CONFIG_SF_DEFAULT_BUS 0 52 #define CONFIG_SF_DEFAULT_CS 0 53 #define CONFIG_SF_DEFAULT_SPEED 25000000 54 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 55 56 /* MTD support */ 57 #ifndef CONFIG_SPL_BUILD 58 #define CONFIG_MTD_DEVICE 59 #define CONFIG_MTD_PARTITIONS 60 #define CONFIG_SPI_FLASH_MTD 61 #endif 62 63 #define MTDIDS_DEFAULT "nor0=spi0.0" 64 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:" \ 65 "768k(uboot)," \ 66 "256k(uboot-environment)," \ 67 "-(reserved)" 68 69 /* Environment */ 70 #define CONFIG_ENV_IS_IN_SPI_FLASH 71 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 72 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 73 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 74 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 75 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 76 #define CONFIG_ENV_SIZE (8 * 1024) 77 #define CONFIG_ENV_OFFSET (768 * 1024) 78 79 #define CONFIG_EXTRA_ENV_SETTINGS \ 80 "stdin=serial,usbkbd\0" \ 81 "stdout=serial,vga\0" \ 82 "stderr=serial,vga\0" \ 83 "panel=HDMI\0" \ 84 "autoload=no\0" \ 85 "uImage=uImage-cm-fx6\0" \ 86 "zImage=zImage-cm-fx6\0" \ 87 "kernel=uImage-cm-fx6\0" \ 88 "script=boot.scr\0" \ 89 "dtb=cm-fx6.dtb\0" \ 90 "bootm_low=18000000\0" \ 91 "loadaddr=0x10800000\0" \ 92 "fdtaddr=0x11000000\0" \ 93 "console=ttymxc3,115200\0" \ 94 "ethprime=FEC0\0" \ 95 "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ 96 "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ 97 "doboot=bootm ${loadaddr}\0" \ 98 "doloadfdt=false\0" \ 99 "mtdids=" MTDIDS_DEFAULT "\0" \ 100 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 101 "setboottypez=setenv kernel ${zImage};" \ 102 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ 103 "setenv doloadfdt true;\0" \ 104 "setboottypem=setenv kernel ${uImage};" \ 105 "setenv doboot bootm ${loadaddr};" \ 106 "setenv doloadfdt false;\0"\ 107 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 108 "sataroot=/dev/sda2 rw rootwait\0" \ 109 "nandroot=/dev/mtdblock4 rw\0" \ 110 "nandrootfstype=ubifs\0" \ 111 "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ 112 "${video} ${extrabootargs}\0" \ 113 "sataargs=setenv bootargs console=${console} root=${sataroot} " \ 114 "${video} ${extrabootargs}\0" \ 115 "nandargs=setenv bootargs console=${console} " \ 116 "root=${nandroot} " \ 117 "rootfstype=${nandrootfstype} " \ 118 "${video} ${extrabootargs}\0" \ 119 "nandboot=if run nandloadkernel; then " \ 120 "run nandloadfdt;" \ 121 "run setboottypem;" \ 122 "run storagebootcmd;" \ 123 "run setboottypez;" \ 124 "run storagebootcmd;" \ 125 "fi;\0" \ 126 "run_eboot=echo Starting EBOOT ...; "\ 127 "mmc dev 2 && " \ 128 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ 129 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ 130 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ 131 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ 132 "bootscript=echo Running bootscript from ${storagetype} ...;" \ 133 "source ${loadaddr};\0" \ 134 "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ 135 "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ 136 "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ 137 "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ 138 "setupnandboot=setenv storagetype nand;\0" \ 139 "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ 140 "storagebootcmd=echo Booting from ${storagetype} ...;" \ 141 "run ${storagetype}args; run doboot;\0" \ 142 "trybootk=if run loadkernel; then " \ 143 "if ${doloadfdt}; then " \ 144 "run loadfdt;" \ 145 "fi;" \ 146 "run storagebootcmd;" \ 147 "fi;\0" \ 148 "trybootsmz=if run loadscript; then " \ 149 "run bootscript;" \ 150 "fi;" \ 151 "run setboottypem;" \ 152 "run trybootk;" \ 153 "run setboottypez;" \ 154 "run trybootk;\0" 155 156 #define CONFIG_BOOTCOMMAND \ 157 "run setupmmcboot;" \ 158 "mmc dev ${storagedev};" \ 159 "if mmc rescan; then " \ 160 "run trybootsmz;" \ 161 "fi;" \ 162 "run setupusbboot;" \ 163 "if usb start; then "\ 164 "if run loadscript; then " \ 165 "run bootscript;" \ 166 "fi;" \ 167 "fi;" \ 168 "run setupsataboot;" \ 169 "if sata init; then " \ 170 "run trybootsmz;" \ 171 "fi;" \ 172 "run setupnandboot;" \ 173 "run nandboot;" 174 175 #define CONFIG_PREBOOT "usb start;sf probe" 176 177 /* SPI */ 178 #define CONFIG_SPI 179 #define CONFIG_MXC_SPI 180 181 /* NAND */ 182 #ifndef CONFIG_SPL_BUILD 183 #define CONFIG_CMD_NAND 184 #define CONFIG_SYS_NAND_BASE 0x40000000 185 #define CONFIG_SYS_NAND_MAX_CHIPS 1 186 #define CONFIG_SYS_MAX_NAND_DEVICE 1 187 #define CONFIG_NAND_MXS 188 #define CONFIG_SYS_NAND_ONFI_DETECTION 189 /* APBH DMA is required for NAND support */ 190 #define CONFIG_APBH_DMA 191 #define CONFIG_APBH_DMA_BURST 192 #define CONFIG_APBH_DMA_BURST8 193 #endif 194 195 /* Ethernet */ 196 #define CONFIG_FEC_MXC 197 #define CONFIG_FEC_MXC_PHYADDR 0 198 #define CONFIG_FEC_XCV_TYPE RGMII 199 #define IMX_FEC_BASE ENET_BASE_ADDR 200 #define CONFIG_PHYLIB 201 #define CONFIG_PHY_ATHEROS 202 #define CONFIG_MII 203 #define CONFIG_ETHPRIME "FEC0" 204 #define CONFIG_ARP_TIMEOUT 200UL 205 #define CONFIG_NET_RETRY_COUNT 5 206 207 /* USB */ 208 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 209 #define CONFIG_MXC_USB_FLAGS 0 210 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 211 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 212 213 /* I2C */ 214 #define CONFIG_SYS_I2C 215 #define CONFIG_SYS_I2C_MXC 216 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 217 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 218 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 219 #define CONFIG_SYS_I2C_SPEED 100000 220 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 221 222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 223 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 224 #define CONFIG_SYS_I2C_EEPROM_BUS 2 225 226 /* SATA */ 227 #define CONFIG_CMD_SATA 228 #define CONFIG_SYS_SATA_MAX_DEVICE 1 229 #define CONFIG_LIBATA 230 #define CONFIG_LBA48 231 #define CONFIG_DWC_AHSATA 232 #define CONFIG_DWC_AHSATA_PORT_ID 0 233 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 234 235 /* Boot */ 236 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 237 #define CONFIG_SERIAL_TAG 238 239 /* misc */ 240 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 241 #define CONFIG_MISC_INIT_R 242 243 /* SPL */ 244 #include "imx6_spl.h" 245 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 246 #define CONFIG_SPL_SPI_LOAD 247 248 /* Display */ 249 #define CONFIG_VIDEO_IPUV3 250 #define CONFIG_IPUV3_CLK 260000000 251 #define CONFIG_IMX_HDMI 252 253 #define CONFIG_SPLASH_SCREEN 254 #define CONFIG_SPLASH_SOURCE 255 #define CONFIG_VIDEO_BMP_RLE8 256 257 #define CONFIG_VIDEO_LOGO 258 #define CONFIG_VIDEO_BMP_LOGO 259 260 /* EEPROM */ 261 #define CONFIG_ENV_EEPROM_IS_ON_I2C 262 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 264 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 265 #define CONFIG_SYS_EEPROM_SIZE 256 266 267 #endif /* __CONFIG_CM_FX6_H */ 268