1 /* 2 * Config file for Compulab CM-FX6 board 3 * 4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ 5 * 6 * Author: Nikita Kiryanov <nikita@compulab.co.il> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_CM_FX6_H 12 #define __CONFIG_CM_FX6_H 13 14 #include <asm/arch/imx-regs.h> 15 #include <config_distro_defaults.h> 16 #include "mx6_common.h" 17 18 /* Machine config */ 19 #define CONFIG_MX6 20 #define CONFIG_SYS_LITTLE_ENDIAN 21 #define CONFIG_MACH_TYPE 4273 22 23 #ifndef CONFIG_SPL_BUILD 24 #define CONFIG_CMD_GPIO 25 #endif 26 27 /* Display information on boot */ 28 #define CONFIG_DISPLAY_CPUINFO 29 #define CONFIG_DISPLAY_BOARDINFO 30 #define CONFIG_TIMESTAMP 31 32 /* CMD */ 33 #include <config_cmd_default.h> 34 #define CONFIG_CMD_GREPENV 35 #undef CONFIG_CMD_FLASH 36 #undef CONFIG_CMD_LOADB 37 #undef CONFIG_CMD_LOADS 38 #undef CONFIG_CMD_XIMG 39 #undef CONFIG_CMD_FPGA 40 #undef CONFIG_CMD_IMLS 41 42 /* MMC */ 43 #define CONFIG_MMC 44 #define CONFIG_CMD_MMC 45 #define CONFIG_GENERIC_MMC 46 #define CONFIG_FSL_ESDHC 47 #define CONFIG_FSL_USDHC 48 #define CONFIG_SYS_FSL_USDHC_NUM 3 49 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR 50 51 /* RAM */ 52 #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR 53 #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR 54 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 55 #define CONFIG_NR_DRAM_BANKS 2 56 #define CONFIG_SYS_MEMTEST_START 0x10000000 57 #define CONFIG_SYS_MEMTEST_END 0x10010000 58 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 59 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 60 #define CONFIG_SYS_INIT_SP_OFFSET \ 61 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 62 #define CONFIG_SYS_INIT_SP_ADDR \ 63 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 64 65 /* Serial console */ 66 #define CONFIG_MXC_UART 67 #define CONFIG_MXC_UART_BASE UART4_BASE 68 #define CONFIG_BAUDRATE 115200 69 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 70 71 /* Shell */ 72 #define CONFIG_SYS_PROMPT "CM-FX6 # " 73 #define CONFIG_SYS_CBSIZE 1024 74 #define CONFIG_SYS_MAXARGS 16 75 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 76 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 77 sizeof(CONFIG_SYS_PROMPT) + 16) 78 79 /* SPI flash */ 80 #define CONFIG_SYS_NO_FLASH 81 #define CONFIG_CMD_SF 82 #define CONFIG_SF_DEFAULT_BUS 0 83 #define CONFIG_SF_DEFAULT_CS 0 84 #define CONFIG_SF_DEFAULT_SPEED 25000000 85 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 86 87 /* Environment */ 88 #define CONFIG_ENV_OVERWRITE 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 91 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 92 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 93 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 94 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 95 #define CONFIG_ENV_SIZE (8 * 1024) 96 #define CONFIG_ENV_OFFSET (768 * 1024) 97 98 #define CONFIG_EXTRA_ENV_SETTINGS \ 99 "stdin=serial,usbkbd\0" \ 100 "stdout=serial,vga\0" \ 101 "stderr=serial,vga\0" \ 102 "panel=HDMI\0" \ 103 "autoload=no\0" \ 104 "kernel=uImage-cm-fx6\0" \ 105 "script=boot.scr\0" \ 106 "dtb=cm-fx6.dtb\0" \ 107 "bootm_low=18000000\0" \ 108 "loadaddr=0x10800000\0" \ 109 "fdtaddr=0x11000000\0" \ 110 "console=ttymxc3,115200\0" \ 111 "ethprime=FEC0\0" \ 112 "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ 113 "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ 114 "doboot=bootm ${loadaddr}\0" \ 115 "doloadfdt=false\0" \ 116 "setboottypez=setenv kernel zImage-cm-fx6;" \ 117 "setenv doboot bootz ${loadaddr} - ${fdtaddr};" \ 118 "setenv doloadfdt true;\0" \ 119 "setboottypem=setenv kernel uImage-cm-fx6;" \ 120 "setenv doboot bootm ${loadaddr};" \ 121 "setenv doloadfdt false;\0"\ 122 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 123 "sataroot=/dev/sda2 rw rootwait\0" \ 124 "nandroot=/dev/mtdblock4 rw\0" \ 125 "nandrootfstype=ubifs\0" \ 126 "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ 127 "${video}\0" \ 128 "sataargs=setenv bootargs console=${console} root=${sataroot} " \ 129 "${video}\0" \ 130 "nandargs=setenv bootargs console=${console} " \ 131 "root=${nandroot} " \ 132 "rootfstype=${nandrootfstype} " \ 133 "${video}\0" \ 134 "nandboot=if run nandloadkernel; then " \ 135 "run nandloadfdt;" \ 136 "run setboottypem;" \ 137 "run storagebootcmd;" \ 138 "run setboottypez;" \ 139 "run storagebootcmd;" \ 140 "fi;\0" \ 141 "run_eboot=echo Starting EBOOT ...; "\ 142 "mmc dev 2 && " \ 143 "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ 144 "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0"\ 145 "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0"\ 146 "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${dtb};\0" \ 147 "bootscript=echo Running bootscript from ${storagetype} ...;" \ 148 "source ${loadaddr};\0" \ 149 "nandloadkernel=nand read ${loadaddr} 0 780000;\0" \ 150 "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \ 151 "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ 152 "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ 153 "setupnandboot=setenv storagetype nand;\0" \ 154 "setupusbboot=setenv storagetype usb; setenv storagedev 0;\0" \ 155 "storagebootcmd=echo Booting from ${storagetype} ...;" \ 156 "run ${storagetype}args; run doboot;\0" \ 157 "trybootk=if run loadkernel; then " \ 158 "if ${doloadfdt}; then " \ 159 "run loadfdt;" \ 160 "fi;" \ 161 "run storagebootcmd;" \ 162 "fi;\0" \ 163 "trybootsmz=if run loadscript; then " \ 164 "run bootscript;" \ 165 "fi;" \ 166 "run setboottypem;" \ 167 "run trybootk;" \ 168 "run setboottypez;" \ 169 "run trybootk;\0" 170 171 #define CONFIG_BOOTCOMMAND \ 172 "run setupmmcboot;" \ 173 "mmc dev ${storagedev};" \ 174 "if mmc rescan; then " \ 175 "run trybootsmz;" \ 176 "fi;" \ 177 "run setupusbboot;" \ 178 "if usb start; then "\ 179 "if run loadscript; then " \ 180 "run bootscript;" \ 181 "fi;" \ 182 "fi;" \ 183 "run setupsataboot;" \ 184 "if sata init; then " \ 185 "run trybootsmz;" \ 186 "fi;" \ 187 "run setupnandboot;" \ 188 "run nandboot;" 189 190 #define CONFIG_PREBOOT "usb start" 191 192 /* SPI */ 193 #define CONFIG_SPI 194 #define CONFIG_MXC_SPI 195 #define CONFIG_SPI_FLASH 196 #define CONFIG_SPI_FLASH_ATMEL 197 #define CONFIG_SPI_FLASH_EON 198 #define CONFIG_SPI_FLASH_GIGADEVICE 199 #define CONFIG_SPI_FLASH_MACRONIX 200 #define CONFIG_SPI_FLASH_SPANSION 201 #define CONFIG_SPI_FLASH_STMICRO 202 #define CONFIG_SPI_FLASH_SST 203 #define CONFIG_SPI_FLASH_WINBOND 204 205 /* NAND */ 206 #ifndef CONFIG_SPL_BUILD 207 #define CONFIG_CMD_NAND 208 #define CONFIG_SYS_NAND_BASE 0x40000000 209 #define CONFIG_SYS_NAND_MAX_CHIPS 1 210 #define CONFIG_SYS_MAX_NAND_DEVICE 1 211 #define CONFIG_NAND_MXS 212 #define CONFIG_SYS_NAND_ONFI_DETECTION 213 /* APBH DMA is required for NAND support */ 214 #define CONFIG_APBH_DMA 215 #define CONFIG_APBH_DMA_BURST 216 #define CONFIG_APBH_DMA_BURST8 217 #endif 218 219 /* Ethernet */ 220 #define CONFIG_FEC_MXC 221 #define CONFIG_FEC_MXC_PHYADDR 0 222 #define CONFIG_FEC_XCV_TYPE RGMII 223 #define IMX_FEC_BASE ENET_BASE_ADDR 224 #define CONFIG_PHYLIB 225 #define CONFIG_PHY_ATHEROS 226 #define CONFIG_MII 227 #define CONFIG_ETHPRIME "FEC0" 228 #define CONFIG_ARP_TIMEOUT 200UL 229 #define CONFIG_NET_RETRY_COUNT 5 230 231 /* USB */ 232 #define CONFIG_CMD_USB 233 #define CONFIG_USB_EHCI 234 #define CONFIG_USB_EHCI_MX6 235 #define CONFIG_USB_STORAGE 236 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 237 #define CONFIG_MXC_USB_FLAGS 0 238 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 239 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 240 #define CONFIG_USB_KEYBOARD 241 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 242 #define CONFIG_SYS_STDIO_DEREGISTER 243 244 /* I2C */ 245 #define CONFIG_CMD_I2C 246 #define CONFIG_SYS_I2C 247 #define CONFIG_SYS_I2C_MXC 248 #define CONFIG_SYS_I2C_SPEED 100000 249 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 250 251 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 253 #define CONFIG_SYS_I2C_EEPROM_BUS 2 254 255 /* SATA */ 256 #define CONFIG_CMD_SATA 257 #define CONFIG_SYS_SATA_MAX_DEVICE 1 258 #define CONFIG_LIBATA 259 #define CONFIG_LBA48 260 #define CONFIG_DWC_AHSATA 261 #define CONFIG_DWC_AHSATA_PORT_ID 0 262 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 263 264 /* GPIO */ 265 #define CONFIG_MXC_GPIO 266 267 /* Boot */ 268 #define CONFIG_ZERO_BOOTDELAY_CHECK 269 #define CONFIG_LOADADDR 0x10800000 270 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 271 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 272 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 273 #define CONFIG_SETUP_MEMORY_TAGS 274 #define CONFIG_INITRD_TAG 275 #define CONFIG_REVISION_TAG 276 #define CONFIG_SERIAL_TAG 277 278 /* misc */ 279 #define CONFIG_SYS_GENERIC_BOARD 280 #define CONFIG_STACKSIZE (128 * 1024) 281 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 282 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 283 #define CONFIG_OF_BOARD_SETUP 284 285 /* SPL */ 286 #include "imx6_spl.h" 287 #define CONFIG_SPL_BOARD_INIT 288 #define CONFIG_SPL_MMC_SUPPORT 289 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 /* offset 64 kb */ 290 #define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS / 2 * 1024) 291 #define CONFIG_SPL_SPI_SUPPORT 292 #define CONFIG_SPL_SPI_FLASH_SUPPORT 293 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 294 #define CONFIG_SPL_SPI_LOAD 295 296 /* Display */ 297 #define CONFIG_VIDEO 298 #define CONFIG_VIDEO_IPUV3 299 #define CONFIG_IPUV3_CLK 260000000 300 #define CONFIG_IMX_HDMI 301 #define CONFIG_IMX_VIDEO_SKIP 302 #define CONFIG_CFB_CONSOLE 303 #define CONFIG_VGA_AS_SINGLE_DEVICE 304 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 305 #define CONFIG_CONSOLE_MUX 306 #define CONFIG_VIDEO_SW_CURSOR 307 308 #define CONFIG_SPLASH_SCREEN 309 #define CONFIG_SPLASH_SOURCE 310 #define CONFIG_CMD_BMP 311 #define CONFIG_VIDEO_BMP_RLE8 312 313 #define CONFIG_VIDEO_LOGO 314 #define CONFIG_VIDEO_BMP_LOGO 315 316 #endif /* __CONFIG_CM_FX6_H */ 317