1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * CI20 configuration 4 * 5 * Copyright (c) 2013 Imagination Technologies 6 * Author: Paul Burton <paul.burton@imgtec.com> 7 */ 8 9 #ifndef __CONFIG_CI20_H__ 10 #define __CONFIG_CI20_H__ 11 12 #define CONFIG_SKIP_LOWLEVEL_INIT 13 14 /* Ingenic JZ4780 clock configuration. */ 15 #define CONFIG_SYS_HZ 1000 16 #define CONFIG_SYS_MHZ 1200 17 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 18 19 /* Memory configuration */ 20 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 21 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 22 #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) 23 24 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ 25 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 26 #define CONFIG_SYS_LOAD_ADDR 0x81000000 27 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 28 #define CONFIG_SYS_MEMTEST_START 0x80000000 29 #define CONFIG_SYS_MEMTEST_END 0x88000000 30 31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 32 33 /* NS16550-ish UARTs */ 34 #define CONFIG_SYS_NS16550_CLK 48000000 35 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 36 37 /* Ethernet: davicom DM9000 */ 38 #define CONFIG_DRIVER_DM9000 1 39 #define CONFIG_DM9000_BASE 0xb6000000 40 #define DM9000_IO CONFIG_DM9000_BASE 41 #define DM9000_DATA (CONFIG_DM9000_BASE + 2) 42 43 /* Environment */ 44 #define CONFIG_SYS_MMC_ENV_DEV 0 45 #define CONFIG_ENV_SIZE (32 << 10) 46 #define CONFIG_ENV_OFFSET ((14 + 512) << 10) 47 #define CONFIG_ENV_OVERWRITE 48 49 /* Command line configuration. */ 50 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 51 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 52 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 53 /* Boot argument buffer size */ 54 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 55 56 /* Miscellaneous configuration options */ 57 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 58 59 /* SPL */ 60 #define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ 61 62 #define CONFIG_SPL_TEXT_BASE 0xf4000a00 63 #define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) 64 65 #define CONFIG_SPL_BSS_START_ADDR 0xf4004000 66 #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ 67 68 #define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" 69 70 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */ 71 72 #endif /* __CONFIG_CI20_H__ */ 73