1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2008 4 * Graeme Russ, graeme.russ@gmail.com. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 #include <configs/x86-common.h> 17 18 #define CONFIG_SYS_CAR_ADDR 0xff7e0000 19 #define CONFIG_SYS_CAR_SIZE (128 * 1024) 20 #define CONFIG_SYS_MONITOR_LEN (1 << 20) 21 #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 22 #define CONFIG_BOARD_EARLY_INIT_F 23 #define CONFIG_DISPLAY_CPUINFO 24 25 #define CONFIG_NR_DRAM_BANKS 8 26 #define CONFIG_X86_MRC_ADDR 0xfffa0000 27 #define CONFIG_CACHE_MRC_SIZE_KB 512 28 29 #define CONFIG_X86_SERIAL 30 31 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ 32 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ 33 {PCI_VENDOR_ID_INTEL, \ 34 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ 35 {PCI_VENDOR_ID_INTEL, \ 36 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ 37 {PCI_VENDOR_ID_INTEL, \ 38 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} 39 40 #define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin 41 #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 42 #define CONFIG_VIDEO_X86 43 44 #define CONFIG_PCI_MEM_BUS 0xe0000000 45 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 46 #define CONFIG_PCI_MEM_SIZE 0x10000000 47 48 #define CONFIG_PCI_PREF_BUS 0xd0000000 49 #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS 50 #define CONFIG_PCI_PREF_SIZE 0x10000000 51 52 #define CONFIG_PCI_IO_BUS 0x1000 53 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 54 #define CONFIG_PCI_IO_SIZE 0xefff 55 56 #define CONFIG_SYS_EARLY_PCI_INIT 57 #define CONFIG_PCI_PNP 58 59 #define CONFIG_BIOSEMU 60 #define VIDEO_IO_OFFSET 0 61 #define CONFIG_X86EMU_RAW_IO 62 63 #define CONFIG_CROS_EC 64 #define CONFIG_CROS_EC_LPC 65 #define CONFIG_CMD_CROS_EC 66 #define CONFIG_ARCH_EARLY_INIT_R 67 68 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ 69 "stdout=vga,serial\0" \ 70 "stderr=vga,serial\0" 71 72 #endif /* __CONFIG_H */ 73