1 /* 2 * 3 * Congatec Conga-QEVAl board configuration file. 4 * 5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 6 * Based on Freescale i.MX6Q Sabre Lite board configuration file. 7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 8 * Leo Sartre, <lsartre@adeneo-embedded.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_CGTQMX6EVAL_H 14 #define __CONFIG_CGTQMX6EVAL_H 15 16 #include "mx6_common.h" 17 18 #define CONFIG_MACH_TYPE 4122 19 20 #ifdef CONFIG_SPL 21 #define CONFIG_SPL_LIBCOMMON_SUPPORT 22 #define CONFIG_SPL_MMC_SUPPORT 23 #define CONFIG_SPL_SPI_SUPPORT 24 #define CONFIG_SPL_SPI_FLASH_SUPPORT 25 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 26 #define CONFIG_SPL_SPI_LOAD 27 #include "imx6_spl.h" 28 #endif 29 30 /* Size of malloc() pool */ 31 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 32 33 #define CONFIG_BOARD_EARLY_INIT_F 34 #define CONFIG_BOARD_LATE_INIT 35 #define CONFIG_MISC_INIT_R 36 37 #define CONFIG_MXC_UART 38 #define CONFIG_MXC_UART_BASE UART2_BASE 39 40 /* MMC Configs */ 41 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 42 43 /* SPI NOR */ 44 #define CONFIG_CMD_SF 45 #define CONFIG_SPI_FLASH 46 #define CONFIG_SPI_FLASH_STMICRO 47 #define CONFIG_SPI_FLASH_SST 48 #define CONFIG_MXC_SPI 49 #define CONFIG_SF_DEFAULT_BUS 0 50 #define CONFIG_SF_DEFAULT_SPEED 20000000 51 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 52 53 /* Miscellaneous commands */ 54 #define CONFIG_CMD_BMODE 55 56 /* Thermal support */ 57 #define CONFIG_IMX_THERMAL 58 59 /* I2C Configs */ 60 #define CONFIG_CMD_I2C 61 #define CONFIG_SYS_I2C 62 #define CONFIG_SYS_I2C_MXC 63 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 64 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 65 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 66 #define CONFIG_SYS_I2C_SPEED 100000 67 68 /* PMIC */ 69 #define CONFIG_POWER 70 #define CONFIG_POWER_I2C 71 #define CONFIG_POWER_PFUZE100 72 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 73 74 /* USB Configs */ 75 #define CONFIG_CMD_USB 76 #define CONFIG_CMD_FAT 77 #define CONFIG_USB_EHCI 78 #define CONFIG_USB_EHCI_MX6 79 #define CONFIG_USB_STORAGE 80 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 81 #define CONFIG_USB_HOST_ETHER 82 #define CONFIG_USB_ETHER_ASIX 83 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 84 #define CONFIG_MXC_USB_FLAGS 0 85 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 86 #define CONFIG_USB_KEYBOARD 87 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 88 89 #define CONFIG_CI_UDC 90 #define CONFIG_USBD_HS 91 #define CONFIG_USB_GADGET_DUALSPEED 92 93 #define CONFIG_CMD_USB_MASS_STORAGE 94 #define CONFIG_USB_FUNCTION_MASS_STORAGE 95 #define CONFIG_USB_GADGET_DOWNLOAD 96 #define CONFIG_USB_GADGET_VBUS_DRAW 2 97 98 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 99 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 100 #define CONFIG_G_DNL_MANUFACTURER "Congatec" 101 102 /* USB Device Firmware Update support */ 103 #define CONFIG_CMD_DFU 104 #define CONFIG_USB_FUNCTION_DFU 105 #define CONFIG_DFU_MMC 106 #define CONFIG_DFU_SF 107 108 #define CONFIG_USB_FUNCTION_FASTBOOT 109 #define CONFIG_CMD_FASTBOOT 110 #define CONFIG_ANDROID_BOOT_IMAGE 111 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 112 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 113 114 /* Framebuffer */ 115 #define CONFIG_VIDEO 116 #define CONFIG_VIDEO_IPUV3 117 #define CONFIG_CFB_CONSOLE 118 #define CONFIG_VGA_AS_SINGLE_DEVICE 119 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 120 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 121 #define CONFIG_VIDEO_BMP_RLE8 122 #define CONFIG_SPLASH_SCREEN 123 #define CONFIG_SPLASH_SCREEN_ALIGN 124 #define CONFIG_BMP_16BPP 125 #define CONFIG_VIDEO_LOGO 126 #define CONFIG_VIDEO_BMP_LOGO 127 #ifdef CONFIG_MX6DL 128 #define CONFIG_IPUV3_CLK 198000000 129 #else 130 #define CONFIG_IPUV3_CLK 264000000 131 #endif 132 #define CONFIG_IMX_HDMI 133 134 /* SATA */ 135 #define CONFIG_CMD_SATA 136 #define CONFIG_DWC_AHSATA 137 #define CONFIG_SYS_SATA_MAX_DEVICE 1 138 #define CONFIG_DWC_AHSATA_PORT_ID 0 139 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 140 #define CONFIG_LBA48 141 #define CONFIG_LIBATA 142 143 /* Ethernet */ 144 #define CONFIG_CMD_PING 145 #define CONFIG_CMD_DHCP 146 #define CONFIG_CMD_MII 147 #define CONFIG_FEC_MXC 148 #define CONFIG_MII 149 #define IMX_FEC_BASE ENET_BASE_ADDR 150 #define CONFIG_FEC_XCV_TYPE RGMII 151 #define CONFIG_ETHPRIME "FEC" 152 #define CONFIG_FEC_MXC_PHYADDR 6 153 #define CONFIG_PHYLIB 154 #define CONFIG_PHY_ATHEROS 155 156 /* Command definition */ 157 158 #define CONFIG_MXC_UART_BASE UART2_BASE 159 #define CONFIG_CONSOLE_DEV "ttymxc1" 160 #define CONFIG_MMCROOT "/dev/mmcblk0p2" 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 163 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 164 #define CONFIG_EXTRA_ENV_SETTINGS \ 165 "script=boot.scr\0" \ 166 "image=zImage\0" \ 167 "fdtfile=undefined\0" \ 168 "fdt_addr_r=0x18000000\0" \ 169 "boot_fdt=try\0" \ 170 "ip_dyn=yes\0" \ 171 "console=" CONFIG_CONSOLE_DEV "\0" \ 172 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ 173 "dfu_alt_info_spl=spl raw 0x400\0" \ 174 "dfu_alt_info_img=u-boot raw 0x10000\0" \ 175 "dfu_alt_info=spl raw 0x400\0" \ 176 "bootm_size=0x10000000\0" \ 177 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ 178 "mmcpart=1\0" \ 179 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 180 "update_sd_firmware=" \ 181 "if test ${ip_dyn} = yes; then " \ 182 "setenv get_cmd dhcp; " \ 183 "else " \ 184 "setenv get_cmd tftp; " \ 185 "fi; " \ 186 "if mmc dev ${mmcdev}; then " \ 187 "if ${get_cmd} ${update_sd_firmware_filename}; then " \ 188 "setexpr fw_sz ${filesize} / 0x200; " \ 189 "setexpr fw_sz ${fw_sz} + 1; " \ 190 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ 191 "fi; " \ 192 "fi\0" \ 193 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 194 "root=${mmcroot}\0" \ 195 "loadbootscript=" \ 196 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 197 "bootscript=echo Running bootscript from mmc ...; " \ 198 "source\0" \ 199 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 200 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ 201 "mmcboot=echo Booting from mmc ...; " \ 202 "run mmcargs; " \ 203 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 204 "if run loadfdt; then " \ 205 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 206 "else " \ 207 "if test ${boot_fdt} = try; then " \ 208 "bootz; " \ 209 "else " \ 210 "echo WARN: Cannot load the DT; " \ 211 "fi; " \ 212 "fi; " \ 213 "else " \ 214 "bootz; " \ 215 "fi;\0" \ 216 "findfdt="\ 217 "if test $board_rev = MX6Q ; then " \ 218 "setenv fdtfile imx6q-qmx6.dtb; fi; " \ 219 "if test $board_rev = MX6DL ; then " \ 220 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ 221 "if test $fdtfile = undefined; then " \ 222 "echo WARNING: Could not determine dtb to use; fi; \0" \ 223 "netargs=setenv bootargs console=${console},${baudrate} " \ 224 "root=/dev/nfs " \ 225 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 226 "netboot=echo Booting from net ...; " \ 227 "run netargs; " \ 228 "if test ${ip_dyn} = yes; then " \ 229 "setenv get_cmd dhcp; " \ 230 "else " \ 231 "setenv get_cmd tftp; " \ 232 "fi; " \ 233 "${get_cmd} ${image}; " \ 234 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 235 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ 236 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 237 "else " \ 238 "if test ${boot_fdt} = try; then " \ 239 "bootz; " \ 240 "else " \ 241 "echo WARN: Cannot load the DT; " \ 242 "fi; " \ 243 "fi; " \ 244 "else " \ 245 "bootz; " \ 246 "fi;\0" \ 247 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ 248 249 #define CONFIG_BOOTCOMMAND \ 250 "run spilock;" \ 251 "run findfdt; " \ 252 "mmc dev ${mmcdev};" \ 253 "if mmc rescan; then " \ 254 "if run loadbootscript; then " \ 255 "run bootscript; " \ 256 "else " \ 257 "if run loadimage; then " \ 258 "run mmcboot; " \ 259 "else run netboot; " \ 260 "fi; " \ 261 "fi; " \ 262 "else run netboot; fi" 263 264 #define CONFIG_SYS_MEMTEST_START 0x10000000 265 #define CONFIG_SYS_MEMTEST_END 0x10010000 266 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 267 268 /* Physical Memory Map */ 269 #define CONFIG_NR_DRAM_BANKS 1 270 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 271 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 272 273 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 274 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 275 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 276 277 #define CONFIG_SYS_INIT_SP_OFFSET \ 278 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_ADDR \ 280 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 281 282 /* Environment organization */ 283 #if defined (CONFIG_ENV_IS_IN_MMC) 284 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 285 #define CONFIG_SYS_MMC_ENV_DEV 0 286 #endif 287 288 #define CONFIG_ENV_SIZE (8 * 1024) 289 290 #define CONFIG_ENV_IS_IN_SPI_FLASH 291 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 292 #define CONFIG_ENV_OFFSET (768 * 1024) 293 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 294 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 295 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 296 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 297 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 298 #endif 299 300 #endif /* __CONFIG_CGTQMX6EVAL_H */ 301