1 /* 2 * 3 * Congatec Conga-QEVAl board configuration file. 4 * 5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 6 * Based on Freescale i.MX6Q Sabre Lite board configuration file. 7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 8 * Leo Sartre, <lsartre@adeneo-embedded.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_CGTQMX6EVAL_H 14 #define __CONFIG_CGTQMX6EVAL_H 15 16 #include "mx6_common.h" 17 18 #define CONFIG_MACH_TYPE 4122 19 20 /* Size of malloc() pool */ 21 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 22 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_MISC_INIT_R 25 26 #define CONFIG_MXC_UART 27 #define CONFIG_MXC_UART_BASE UART2_BASE 28 29 /* MMC Configs */ 30 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 31 32 /* Miscellaneous commands */ 33 #define CONFIG_CMD_BMODE 34 35 /* Thermal support */ 36 #define CONFIG_IMX6_THERMAL 37 38 #define CONFIG_CMD_FUSE 39 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) 40 #define CONFIG_MXC_OCOTP 41 #endif 42 43 /* I2C Configs */ 44 #define CONFIG_CMD_I2C 45 #define CONFIG_SYS_I2C 46 #define CONFIG_SYS_I2C_MXC 47 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 48 #define CONFIG_SYS_I2C_SPEED 100000 49 50 /* PMIC */ 51 #define CONFIG_POWER 52 #define CONFIG_POWER_I2C 53 #define CONFIG_POWER_PFUZE100 54 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 55 56 /* USB Configs */ 57 #define CONFIG_CMD_USB 58 #define CONFIG_CMD_FAT 59 #define CONFIG_USB_EHCI 60 #define CONFIG_USB_EHCI_MX6 61 #define CONFIG_USB_STORAGE 62 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 63 #define CONFIG_USB_HOST_ETHER 64 #define CONFIG_USB_ETHER_ASIX 65 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 66 #define CONFIG_MXC_USB_FLAGS 0 67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 68 #define CONFIG_USB_KEYBOARD 69 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 70 71 /* Framebuffer */ 72 #define CONFIG_VIDEO 73 #define CONFIG_VIDEO_IPUV3 74 #define CONFIG_CFB_CONSOLE 75 #define CONFIG_VGA_AS_SINGLE_DEVICE 76 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 77 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 78 #define CONFIG_VIDEO_BMP_RLE8 79 #define CONFIG_SPLASH_SCREEN 80 #define CONFIG_SPLASH_SCREEN_ALIGN 81 #define CONFIG_BMP_16BPP 82 #define CONFIG_VIDEO_LOGO 83 #define CONFIG_VIDEO_BMP_LOGO 84 #ifdef CONFIG_MX6DL 85 #define CONFIG_IPUV3_CLK 198000000 86 #else 87 #define CONFIG_IPUV3_CLK 264000000 88 #endif 89 #define CONFIG_IMX_HDMI 90 91 /* SATA */ 92 #define CONFIG_CMD_SATA 93 #define CONFIG_DWC_AHSATA 94 #define CONFIG_SYS_SATA_MAX_DEVICE 1 95 #define CONFIG_DWC_AHSATA_PORT_ID 0 96 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 97 #define CONFIG_LBA48 98 #define CONFIG_LIBATA 99 100 /* Ethernet */ 101 #define CONFIG_CMD_PING 102 #define CONFIG_CMD_DHCP 103 #define CONFIG_CMD_MII 104 #define CONFIG_FEC_MXC 105 #define CONFIG_MII 106 #define IMX_FEC_BASE ENET_BASE_ADDR 107 #define CONFIG_FEC_XCV_TYPE RGMII 108 #define CONFIG_ETHPRIME "FEC" 109 #define CONFIG_FEC_MXC_PHYADDR 6 110 #define CONFIG_PHYLIB 111 #define CONFIG_PHY_ATHEROS 112 113 /* Command definition */ 114 115 #define CONFIG_MXC_UART_BASE UART2_BASE 116 #define CONFIG_CONSOLE_DEV "ttymxc1" 117 #define CONFIG_MMCROOT "/dev/mmcblk0p2" 118 #define CONFIG_SYS_MMC_ENV_DEV 0 119 120 #define CONFIG_EXTRA_ENV_SETTINGS \ 121 "script=boot.scr\0" \ 122 "image=zImage\0" \ 123 "fdtfile=imx6q-qmx6.dtb\0" \ 124 "fdt_addr_r=0x18000000\0" \ 125 "boot_fdt=try\0" \ 126 "ip_dyn=yes\0" \ 127 "console=" CONFIG_CONSOLE_DEV "\0" \ 128 "bootm_size=0x10000000\0" \ 129 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ 130 "mmcpart=1\0" \ 131 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 132 "update_sd_firmware=" \ 133 "if test ${ip_dyn} = yes; then " \ 134 "setenv get_cmd dhcp; " \ 135 "else " \ 136 "setenv get_cmd tftp; " \ 137 "fi; " \ 138 "if mmc dev ${mmcdev}; then " \ 139 "if ${get_cmd} ${update_sd_firmware_filename}; then " \ 140 "setexpr fw_sz ${filesize} / 0x200; " \ 141 "setexpr fw_sz ${fw_sz} + 1; " \ 142 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ 143 "fi; " \ 144 "fi\0" \ 145 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 146 "root=${mmcroot}\0" \ 147 "loadbootscript=" \ 148 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 149 "bootscript=echo Running bootscript from mmc ...; " \ 150 "source\0" \ 151 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 152 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ 153 "mmcboot=echo Booting from mmc ...; " \ 154 "run mmcargs; " \ 155 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 156 "if run loadfdt; then " \ 157 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 158 "else " \ 159 "if test ${boot_fdt} = try; then " \ 160 "bootz; " \ 161 "else " \ 162 "echo WARN: Cannot load the DT; " \ 163 "fi; " \ 164 "fi; " \ 165 "else " \ 166 "bootz; " \ 167 "fi;\0" \ 168 "netargs=setenv bootargs console=${console},${baudrate} " \ 169 "root=/dev/nfs " \ 170 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 171 "netboot=echo Booting from net ...; " \ 172 "run netargs; " \ 173 "if test ${ip_dyn} = yes; then " \ 174 "setenv get_cmd dhcp; " \ 175 "else " \ 176 "setenv get_cmd tftp; " \ 177 "fi; " \ 178 "${get_cmd} ${image}; " \ 179 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 180 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ 181 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 182 "else " \ 183 "if test ${boot_fdt} = try; then " \ 184 "bootz; " \ 185 "else " \ 186 "echo WARN: Cannot load the DT; " \ 187 "fi; " \ 188 "fi; " \ 189 "else " \ 190 "bootz; " \ 191 "fi;\0" \ 192 193 #define CONFIG_BOOTCOMMAND \ 194 "mmc dev ${mmcdev};" \ 195 "if mmc rescan; then " \ 196 "if run loadbootscript; then " \ 197 "run bootscript; " \ 198 "else " \ 199 "if run loadimage; then " \ 200 "run mmcboot; " \ 201 "else run netboot; " \ 202 "fi; " \ 203 "fi; " \ 204 "else run netboot; fi" 205 206 #define CONFIG_SYS_MEMTEST_START 0x10000000 207 #define CONFIG_SYS_MEMTEST_END 0x10010000 208 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 209 210 /* Physical Memory Map */ 211 #define CONFIG_NR_DRAM_BANKS 1 212 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 213 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 214 215 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 216 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 217 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 218 219 #define CONFIG_SYS_INIT_SP_OFFSET \ 220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 221 #define CONFIG_SYS_INIT_SP_ADDR \ 222 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 223 224 /* Environment organization */ 225 #define CONFIG_ENV_SIZE (8 * 1024) 226 227 #define CONFIG_ENV_IS_IN_MMC 228 229 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 230 #define CONFIG_SYS_MMC_ENV_DEV 0 231 232 #endif /* __CONFIG_CGTQMX6EVAL_H */ 233