1 /* 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH 3 * 4 * Based on da850evm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * Board 17 */ 18 #define CONFIG_DRIVER_TI_EMAC 19 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN 20 21 /* 22 * SoC Configuration 23 */ 24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 25 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 26 #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() 27 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 28 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 29 #define CONFIG_SYS_TEXT_BASE 0x60000000 30 #define CONFIG_ARCH_CPU_INIT 31 #define CONFIG_DA8XX_GPIO 32 #define CONFIG_HW_WATCHDOG 33 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE 34 #define CONFIG_SYS_WDT_PERIOD_LOW \ 35 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ 36 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 37 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 38 39 /* 40 * PLL configuration 41 */ 42 #define CONFIG_SYS_DV_CLKMODE 0 43 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 44 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 45 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 46 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 47 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 48 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 49 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 50 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 51 52 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 53 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 54 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 55 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 56 57 #define CONFIG_SYS_DA850_PLL0_PLLM \ 58 ((calimain_get_osc_freq() == 25000000) ? 23 : 24) 59 #define CONFIG_SYS_DA850_PLL1_PLLM \ 60 ((calimain_get_osc_freq() == 25000000) ? 20 : 21) 61 62 /* 63 * DDR2 memory configuration 64 */ 65 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 66 DV_DDR_PHY_EXT_STRBEN | \ 67 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 68 69 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 70 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 71 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 72 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 73 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 74 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 75 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 76 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 77 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 78 79 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 80 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 81 82 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 83 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 84 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 85 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 86 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 87 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 88 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ 89 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 90 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 91 92 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 93 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 94 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 95 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 96 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 97 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 98 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 99 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 100 101 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF 102 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 103 104 /* 105 * Flash memory timing 106 */ 107 108 #define CONFIG_SYS_DA850_CS2CFG ( \ 109 DAVINCI_ABCR_WSETUP(2) | \ 110 DAVINCI_ABCR_WSTROBE(5) | \ 111 DAVINCI_ABCR_WHOLD(3) | \ 112 DAVINCI_ABCR_RSETUP(1) | \ 113 DAVINCI_ABCR_RSTROBE(14) | \ 114 DAVINCI_ABCR_RHOLD(0) | \ 115 DAVINCI_ABCR_TA(3) | \ 116 DAVINCI_ABCR_ASIZE_16BIT) 117 118 /* single 64 MB NOR flash device connected to CS2 and CS3 */ 119 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG 120 121 /* 122 * Memory Info 123 */ 124 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 125 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 126 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 127 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 128 129 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 130 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 131 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 132 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 133 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 134 DAVINCI_SYSCFG_SUSPSRC_I2C) 135 136 /* memtest start addr */ 137 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 138 139 /* memtest will be run on 16MB */ 140 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) 141 142 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 143 144 /* 145 * Serial Driver info 146 */ 147 #define CONFIG_SYS_NS16550_SERIAL 148 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 149 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 150 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 151 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 152 153 #define CONFIG_FLASH_CFI_DRIVER 154 #define CONFIG_SYS_FLASH_CFI 155 #define CONFIG_SYS_FLASH_PROTECTION 156 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 158 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 159 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 160 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 161 #define CONFIG_ENV_ADDR \ 162 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) 163 #define CONFIG_ENV_SIZE (128 << 10) 164 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 165 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 166 #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ 167 #define CONFIG_SYS_MAX_FLASH_SECT \ 168 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) 169 170 /* 171 * Network & Ethernet Configuration 172 */ 173 #ifdef CONFIG_DRIVER_TI_EMAC 174 #define CONFIG_MII 175 #define CONFIG_BOOTP_DNS 176 #define CONFIG_BOOTP_DNS2 177 #define CONFIG_BOOTP_SEND_HOSTNAME 178 #define CONFIG_NET_RETRY_COUNT 10 179 #endif 180 181 /* 182 * U-Boot general configuration 183 */ 184 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 185 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 186 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 187 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 188 #define CONFIG_LOADADDR 0xc0700000 189 #define CONFIG_AUTO_COMPLETE 190 #define CONFIG_CMDLINE_EDITING 191 #define CONFIG_SYS_LONGHELP 192 #define CONFIG_MX_CYCLIC 193 194 /* 195 * Linux Information 196 */ 197 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 198 #define CONFIG_CMDLINE_TAG 199 #define CONFIG_REVISION_TAG 200 #define CONFIG_SETUP_MEMORY_TAGS 201 #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" 202 #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ 203 #define CONFIG_RESET_TO_RETRY 204 205 /* 206 * Default environment settings 207 * gpio0 = button, gpio1 = led green, gpio2 = led red 208 * verify = n ... disable kernel checksum verification for faster booting 209 */ 210 #define CONFIG_EXTRA_ENV_SETTINGS \ 211 "tftpdir=calimero\0" \ 212 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ 213 "erase 0x60800000 +0x400000; " \ 214 "cp.b $loadaddr 0x60800000 $filesize\0" \ 215 "flashrootfs=" \ 216 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ 217 "erase 0x60c00000 +0x2e00000; " \ 218 "cp.b $loadaddr 0x60c00000 $filesize\0" \ 219 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ 220 "protect off all; " \ 221 "erase 0x60000000 +0x80000; " \ 222 "cp.b $loadaddr 0x60000000 $filesize\0" \ 223 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ 224 "erase 0x60080000 +0x780000; " \ 225 "cp.b $loadaddr 0x60080000 $filesize\0" \ 226 "erase_persistent=erase 0x63a00000 +0x600000;\0" \ 227 "bootnor=setenv bootargs console=ttyS2,115200n8 " \ 228 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 229 "rootwait ethaddr=$ethaddr; " \ 230 "gpio c 1; gpio s 2; bootm 0x60800000\0" \ 231 "bootrlk=gpio s 1; gpio s 2;" \ 232 "setenv bootargs console=ttyS2,115200n8 " \ 233 "ethaddr=$ethaddr; bootm 0x60080000\0" \ 234 "boottftp=setenv bootargs console=ttyS2,115200n8 " \ 235 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 236 "rootwait ethaddr=$ethaddr; " \ 237 "tftpboot $loadaddr $tftpdir/uImage;" \ 238 "gpio c 1; gpio s 2; bootm $loadaddr\0" \ 239 "checkupdate=if test -n $update_flag; then " \ 240 "echo Previous update failed - starting RLK; " \ 241 "run bootrlk; fi; " \ 242 "if test -n $initial_setup; then " \ 243 "echo Running initial setup procedure; " \ 244 "sleep 1; run flashall; fi\0" \ 245 "product=accessory\0" \ 246 "serial=XX12345\0" \ 247 "checknor=" \ 248 "if gpio i 0; then run bootnor; fi;\0" \ 249 "checkrlk=" \ 250 "if gpio i 0; then run bootrlk; fi;\0" \ 251 "checkbutton=" \ 252 "run checknor; sleep 1;" \ 253 "run checknor; sleep 1;" \ 254 "run checknor; sleep 1;" \ 255 "run checknor; sleep 1;" \ 256 "run checknor;" \ 257 "gpio s 1; gpio s 2;" \ 258 "echo ---- Release button to boot RLK ----;" \ 259 "run checkrlk; sleep 1;" \ 260 "run checkrlk; sleep 1;" \ 261 "run checkrlk; sleep 1;" \ 262 "run checkrlk; sleep 1;" \ 263 "run checkrlk; sleep 1;" \ 264 "run checkrlk;" \ 265 "echo ---- Factory reset requested ----;" \ 266 "gpio c 1;" \ 267 "setenv factory_reset true;" \ 268 "saveenv;" \ 269 "run bootnor;\0" \ 270 "flashall=run flashrlk;" \ 271 "run flashkernel;" \ 272 "run flashrootfs;" \ 273 "setenv erase_datafs true;" \ 274 "setenv initial_setup;" \ 275 "saveenv;" \ 276 "run bootnor;\0" \ 277 "verify=n\0" \ 278 "clearenv=protect off all;" \ 279 "erase 0x60040000 +0x40000;\0" \ 280 "bootlimit=3\0" \ 281 "altbootcmd=run bootrlk\0" 282 283 #define CONFIG_PREBOOT \ 284 "echo Version: $ver; " \ 285 "echo Serial: $serial; " \ 286 "echo MAC: $ethaddr; " \ 287 "echo Product: $product; " \ 288 "gpio c 1; gpio c 2;" 289 290 /* additions for new relocation code, must added to all boards */ 291 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 292 /* initial stack pointer in internal SRAM */ 293 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) 294 295 #define CONFIG_BOOTCOUNT_LIMIT 296 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ 297 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE 298 299 #ifndef __ASSEMBLY__ 300 int calimain_get_osc_freq(void); 301 #endif 302 303 #include <asm/arch/hardware.h> 304 305 #endif /* __CONFIG_H */ 306