1 /* 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH 3 * 4 * Based on da850evm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * Board 17 */ 18 #define CONFIG_DRIVER_TI_EMAC 19 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN 20 21 /* 22 * SoC Configuration 23 */ 24 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 25 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 26 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 27 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 28 #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() 29 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 30 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 31 #define CONFIG_SYS_TEXT_BASE 0x60000000 32 #define CONFIG_DA850_LOWLEVEL 33 #define CONFIG_ARCH_CPU_INIT 34 #define CONFIG_DA8XX_GPIO 35 #define CONFIG_HW_WATCHDOG 36 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE 37 #define CONFIG_SYS_WDT_PERIOD_LOW \ 38 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ 39 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 40 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 41 42 /* 43 * PLL configuration 44 */ 45 #define CONFIG_SYS_DV_CLKMODE 0 46 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 47 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 48 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 49 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 50 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 51 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 52 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 53 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 54 55 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 56 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 57 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 58 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 59 60 #define CONFIG_SYS_DA850_PLL0_PLLM \ 61 ((calimain_get_osc_freq() == 25000000) ? 23 : 24) 62 #define CONFIG_SYS_DA850_PLL1_PLLM \ 63 ((calimain_get_osc_freq() == 25000000) ? 20 : 21) 64 65 /* 66 * DDR2 memory configuration 67 */ 68 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 69 DV_DDR_PHY_EXT_STRBEN | \ 70 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 71 72 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 73 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 74 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 75 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 76 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 77 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 78 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 79 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 80 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 81 82 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 83 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 84 85 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 86 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 87 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 88 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 89 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 90 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 91 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ 92 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 93 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 94 95 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 96 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 97 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 98 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 99 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 100 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 101 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 102 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 103 104 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF 105 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 106 107 /* 108 * Flash memory timing 109 */ 110 111 #define CONFIG_SYS_DA850_CS2CFG ( \ 112 DAVINCI_ABCR_WSETUP(2) | \ 113 DAVINCI_ABCR_WSTROBE(5) | \ 114 DAVINCI_ABCR_WHOLD(3) | \ 115 DAVINCI_ABCR_RSETUP(1) | \ 116 DAVINCI_ABCR_RSTROBE(14) | \ 117 DAVINCI_ABCR_RHOLD(0) | \ 118 DAVINCI_ABCR_TA(3) | \ 119 DAVINCI_ABCR_ASIZE_16BIT) 120 121 /* single 64 MB NOR flash device connected to CS2 and CS3 */ 122 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG 123 124 /* 125 * Memory Info 126 */ 127 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 128 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 129 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 130 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 131 132 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 133 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 134 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 135 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 136 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 137 DAVINCI_SYSCFG_SUSPSRC_I2C) 138 139 /* memtest start addr */ 140 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 141 142 /* memtest will be run on 16MB */ 143 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) 144 145 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 146 147 /* 148 * Serial Driver info 149 */ 150 #define CONFIG_SYS_NS16550_SERIAL 151 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 152 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 153 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 154 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 155 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_CFI 158 #define CONFIG_SYS_FLASH_PROTECTION 159 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 161 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 162 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 163 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 164 #define CONFIG_ENV_ADDR \ 165 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) 166 #define CONFIG_ENV_SIZE (128 << 10) 167 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 168 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 169 #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ 170 #define CONFIG_SYS_MAX_FLASH_SECT \ 171 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) 172 173 /* 174 * Network & Ethernet Configuration 175 */ 176 #ifdef CONFIG_DRIVER_TI_EMAC 177 #define CONFIG_MII 178 #define CONFIG_BOOTP_DNS 179 #define CONFIG_BOOTP_DNS2 180 #define CONFIG_BOOTP_SEND_HOSTNAME 181 #define CONFIG_NET_RETRY_COUNT 10 182 #endif 183 184 /* 185 * U-Boot general configuration 186 */ 187 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 188 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 189 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 190 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 191 #define CONFIG_LOADADDR 0xc0700000 192 #define CONFIG_AUTO_COMPLETE 193 #define CONFIG_CMDLINE_EDITING 194 #define CONFIG_SYS_LONGHELP 195 #define CONFIG_MX_CYCLIC 196 197 /* 198 * Linux Information 199 */ 200 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 201 #define CONFIG_CMDLINE_TAG 202 #define CONFIG_REVISION_TAG 203 #define CONFIG_SETUP_MEMORY_TAGS 204 #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" 205 #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ 206 #define CONFIG_RESET_TO_RETRY 207 208 /* 209 * Default environment settings 210 * gpio0 = button, gpio1 = led green, gpio2 = led red 211 * verify = n ... disable kernel checksum verification for faster booting 212 */ 213 #define CONFIG_EXTRA_ENV_SETTINGS \ 214 "tftpdir=calimero\0" \ 215 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ 216 "erase 0x60800000 +0x400000; " \ 217 "cp.b $loadaddr 0x60800000 $filesize\0" \ 218 "flashrootfs=" \ 219 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ 220 "erase 0x60c00000 +0x2e00000; " \ 221 "cp.b $loadaddr 0x60c00000 $filesize\0" \ 222 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ 223 "protect off all; " \ 224 "erase 0x60000000 +0x80000; " \ 225 "cp.b $loadaddr 0x60000000 $filesize\0" \ 226 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ 227 "erase 0x60080000 +0x780000; " \ 228 "cp.b $loadaddr 0x60080000 $filesize\0" \ 229 "erase_persistent=erase 0x63a00000 +0x600000;\0" \ 230 "bootnor=setenv bootargs console=ttyS2,115200n8 " \ 231 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 232 "rootwait ethaddr=$ethaddr; " \ 233 "gpio c 1; gpio s 2; bootm 0x60800000\0" \ 234 "bootrlk=gpio s 1; gpio s 2;" \ 235 "setenv bootargs console=ttyS2,115200n8 " \ 236 "ethaddr=$ethaddr; bootm 0x60080000\0" \ 237 "boottftp=setenv bootargs console=ttyS2,115200n8 " \ 238 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 239 "rootwait ethaddr=$ethaddr; " \ 240 "tftpboot $loadaddr $tftpdir/uImage;" \ 241 "gpio c 1; gpio s 2; bootm $loadaddr\0" \ 242 "checkupdate=if test -n $update_flag; then " \ 243 "echo Previous update failed - starting RLK; " \ 244 "run bootrlk; fi; " \ 245 "if test -n $initial_setup; then " \ 246 "echo Running initial setup procedure; " \ 247 "sleep 1; run flashall; fi\0" \ 248 "product=accessory\0" \ 249 "serial=XX12345\0" \ 250 "checknor=" \ 251 "if gpio i 0; then run bootnor; fi;\0" \ 252 "checkrlk=" \ 253 "if gpio i 0; then run bootrlk; fi;\0" \ 254 "checkbutton=" \ 255 "run checknor; sleep 1;" \ 256 "run checknor; sleep 1;" \ 257 "run checknor; sleep 1;" \ 258 "run checknor; sleep 1;" \ 259 "run checknor;" \ 260 "gpio s 1; gpio s 2;" \ 261 "echo ---- Release button to boot RLK ----;" \ 262 "run checkrlk; sleep 1;" \ 263 "run checkrlk; sleep 1;" \ 264 "run checkrlk; sleep 1;" \ 265 "run checkrlk; sleep 1;" \ 266 "run checkrlk; sleep 1;" \ 267 "run checkrlk;" \ 268 "echo ---- Factory reset requested ----;" \ 269 "gpio c 1;" \ 270 "setenv factory_reset true;" \ 271 "saveenv;" \ 272 "run bootnor;\0" \ 273 "flashall=run flashrlk;" \ 274 "run flashkernel;" \ 275 "run flashrootfs;" \ 276 "setenv erase_datafs true;" \ 277 "setenv initial_setup;" \ 278 "saveenv;" \ 279 "run bootnor;\0" \ 280 "verify=n\0" \ 281 "clearenv=protect off all;" \ 282 "erase 0x60040000 +0x40000;\0" \ 283 "bootlimit=3\0" \ 284 "altbootcmd=run bootrlk\0" 285 286 #define CONFIG_PREBOOT \ 287 "echo Version: $ver; " \ 288 "echo Serial: $serial; " \ 289 "echo MAC: $ethaddr; " \ 290 "echo Product: $product; " \ 291 "gpio c 1; gpio c 2;" 292 293 /* additions for new relocation code, must added to all boards */ 294 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 295 /* initial stack pointer in internal SRAM */ 296 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) 297 298 #define CONFIG_BOOTCOUNT_LIMIT 299 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ 300 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE 301 302 #ifndef __ASSEMBLY__ 303 int calimain_get_osc_freq(void); 304 #endif 305 306 #include <asm/arch/hardware.h> 307 308 #endif /* __CONFIG_H */ 309