1 /* 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH 3 * 4 * Based on da850evm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * Board 17 */ 18 #define CONFIG_DRIVER_TI_EMAC 19 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN 20 21 /* 22 * SoC Configuration 23 */ 24 #define CONFIG_MACH_DAVINCI_CALIMAIN 25 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 26 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 27 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 28 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 29 #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() 30 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 31 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 32 #define CONFIG_SYS_TEXT_BASE 0x60000000 33 #define CONFIG_DA850_LOWLEVEL 34 #define CONFIG_ARCH_CPU_INIT 35 #define CONFIG_DA8XX_GPIO 36 #define CONFIG_HW_WATCHDOG 37 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE 38 #define CONFIG_SYS_WDT_PERIOD_LOW \ 39 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ 40 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 41 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 42 43 /* 44 * PLL configuration 45 */ 46 #define CONFIG_SYS_DV_CLKMODE 0 47 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 48 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 49 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 50 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 51 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 52 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 53 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 54 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 55 56 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 57 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 58 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 59 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 60 61 #define CONFIG_SYS_DA850_PLL0_PLLM \ 62 ((calimain_get_osc_freq() == 25000000) ? 23 : 24) 63 #define CONFIG_SYS_DA850_PLL1_PLLM \ 64 ((calimain_get_osc_freq() == 25000000) ? 20 : 21) 65 66 /* 67 * DDR2 memory configuration 68 */ 69 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 70 DV_DDR_PHY_EXT_STRBEN | \ 71 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 72 73 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 74 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 75 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 76 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 77 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 78 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 79 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 80 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 81 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 82 83 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 84 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 85 86 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 87 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 88 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 89 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 90 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 91 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 92 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ 93 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 94 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 95 96 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 97 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 98 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 99 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 100 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 101 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 102 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 103 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 104 105 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF 106 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 107 108 /* 109 * Flash memory timing 110 */ 111 112 #define CONFIG_SYS_DA850_CS2CFG ( \ 113 DAVINCI_ABCR_WSETUP(2) | \ 114 DAVINCI_ABCR_WSTROBE(5) | \ 115 DAVINCI_ABCR_WHOLD(3) | \ 116 DAVINCI_ABCR_RSETUP(1) | \ 117 DAVINCI_ABCR_RSTROBE(14) | \ 118 DAVINCI_ABCR_RHOLD(0) | \ 119 DAVINCI_ABCR_TA(3) | \ 120 DAVINCI_ABCR_ASIZE_16BIT) 121 122 /* single 64 MB NOR flash device connected to CS2 and CS3 */ 123 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG 124 125 /* 126 * Memory Info 127 */ 128 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 129 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 130 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 131 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 132 133 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 134 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 135 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 136 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 137 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 138 DAVINCI_SYSCFG_SUSPSRC_I2C) 139 140 /* memtest start addr */ 141 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 142 143 /* memtest will be run on 16MB */ 144 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) 145 146 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 147 148 /* 149 * Serial Driver info 150 */ 151 #define CONFIG_SYS_NS16550_SERIAL 152 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 153 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 154 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 155 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 156 157 #define CONFIG_FLASH_CFI_DRIVER 158 #define CONFIG_SYS_FLASH_CFI 159 #define CONFIG_SYS_FLASH_PROTECTION 160 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 162 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 163 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 164 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 165 #define CONFIG_ENV_ADDR \ 166 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) 167 #define CONFIG_ENV_SIZE (128 << 10) 168 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 169 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 170 #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ 171 #define CONFIG_SYS_MAX_FLASH_SECT \ 172 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) 173 174 /* 175 * Network & Ethernet Configuration 176 */ 177 #ifdef CONFIG_DRIVER_TI_EMAC 178 #define CONFIG_MII 179 #define CONFIG_BOOTP_DNS 180 #define CONFIG_BOOTP_DNS2 181 #define CONFIG_BOOTP_SEND_HOSTNAME 182 #define CONFIG_NET_RETRY_COUNT 10 183 #endif 184 185 /* 186 * U-Boot general configuration 187 */ 188 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 189 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 190 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 191 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 192 #define CONFIG_LOADADDR 0xc0700000 193 #define CONFIG_AUTO_COMPLETE 194 #define CONFIG_CMDLINE_EDITING 195 #define CONFIG_SYS_LONGHELP 196 #define CONFIG_MX_CYCLIC 197 198 /* 199 * Linux Information 200 */ 201 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 202 #define CONFIG_CMDLINE_TAG 203 #define CONFIG_REVISION_TAG 204 #define CONFIG_SETUP_MEMORY_TAGS 205 #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" 206 #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ 207 #define CONFIG_RESET_TO_RETRY 208 209 /* 210 * Default environment settings 211 * gpio0 = button, gpio1 = led green, gpio2 = led red 212 * verify = n ... disable kernel checksum verification for faster booting 213 */ 214 #define CONFIG_EXTRA_ENV_SETTINGS \ 215 "tftpdir=calimero\0" \ 216 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ 217 "erase 0x60800000 +0x400000; " \ 218 "cp.b $loadaddr 0x60800000 $filesize\0" \ 219 "flashrootfs=" \ 220 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ 221 "erase 0x60c00000 +0x2e00000; " \ 222 "cp.b $loadaddr 0x60c00000 $filesize\0" \ 223 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ 224 "protect off all; " \ 225 "erase 0x60000000 +0x80000; " \ 226 "cp.b $loadaddr 0x60000000 $filesize\0" \ 227 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ 228 "erase 0x60080000 +0x780000; " \ 229 "cp.b $loadaddr 0x60080000 $filesize\0" \ 230 "erase_persistent=erase 0x63a00000 +0x600000;\0" \ 231 "bootnor=setenv bootargs console=ttyS2,115200n8 " \ 232 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 233 "rootwait ethaddr=$ethaddr; " \ 234 "gpio c 1; gpio s 2; bootm 0x60800000\0" \ 235 "bootrlk=gpio s 1; gpio s 2;" \ 236 "setenv bootargs console=ttyS2,115200n8 " \ 237 "ethaddr=$ethaddr; bootm 0x60080000\0" \ 238 "boottftp=setenv bootargs console=ttyS2,115200n8 " \ 239 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 240 "rootwait ethaddr=$ethaddr; " \ 241 "tftpboot $loadaddr $tftpdir/uImage;" \ 242 "gpio c 1; gpio s 2; bootm $loadaddr\0" \ 243 "checkupdate=if test -n $update_flag; then " \ 244 "echo Previous update failed - starting RLK; " \ 245 "run bootrlk; fi; " \ 246 "if test -n $initial_setup; then " \ 247 "echo Running initial setup procedure; " \ 248 "sleep 1; run flashall; fi\0" \ 249 "product=accessory\0" \ 250 "serial=XX12345\0" \ 251 "checknor=" \ 252 "if gpio i 0; then run bootnor; fi;\0" \ 253 "checkrlk=" \ 254 "if gpio i 0; then run bootrlk; fi;\0" \ 255 "checkbutton=" \ 256 "run checknor; sleep 1;" \ 257 "run checknor; sleep 1;" \ 258 "run checknor; sleep 1;" \ 259 "run checknor; sleep 1;" \ 260 "run checknor;" \ 261 "gpio s 1; gpio s 2;" \ 262 "echo ---- Release button to boot RLK ----;" \ 263 "run checkrlk; sleep 1;" \ 264 "run checkrlk; sleep 1;" \ 265 "run checkrlk; sleep 1;" \ 266 "run checkrlk; sleep 1;" \ 267 "run checkrlk; sleep 1;" \ 268 "run checkrlk;" \ 269 "echo ---- Factory reset requested ----;" \ 270 "gpio c 1;" \ 271 "setenv factory_reset true;" \ 272 "saveenv;" \ 273 "run bootnor;\0" \ 274 "flashall=run flashrlk;" \ 275 "run flashkernel;" \ 276 "run flashrootfs;" \ 277 "setenv erase_datafs true;" \ 278 "setenv initial_setup;" \ 279 "saveenv;" \ 280 "run bootnor;\0" \ 281 "verify=n\0" \ 282 "clearenv=protect off all;" \ 283 "erase 0x60040000 +0x40000;\0" \ 284 "bootlimit=3\0" \ 285 "altbootcmd=run bootrlk\0" 286 287 #define CONFIG_PREBOOT \ 288 "echo Version: $ver; " \ 289 "echo Serial: $serial; " \ 290 "echo MAC: $ethaddr; " \ 291 "echo Product: $product; " \ 292 "gpio c 1; gpio c 2;" 293 294 /* additions for new relocation code, must added to all boards */ 295 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 296 /* initial stack pointer in internal SRAM */ 297 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) 298 299 #define CONFIG_BOOTCOUNT_LIMIT 300 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ 301 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE 302 303 #ifndef __ASSEMBLY__ 304 int calimain_get_osc_freq(void); 305 #endif 306 307 #include <asm/arch/hardware.h> 308 309 #endif /* __CONFIG_H */ 310