1 /* 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH 3 * 4 * Based on da850evm.h. Original Copyrights follow: 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * Board 17 */ 18 #define CONFIG_DRIVER_TI_EMAC 19 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN 20 21 /* 22 * SoC Configuration 23 */ 24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 25 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 26 #define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq() 27 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 28 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 29 #define CONFIG_SYS_TEXT_BASE 0x60000000 30 #define CONFIG_ARCH_CPU_INIT 31 #define CONFIG_DA8XX_GPIO 32 #define CONFIG_HW_WATCHDOG 33 #define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE 34 #define CONFIG_SYS_WDT_PERIOD_LOW \ 35 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */ 36 #define CONFIG_SYS_WDT_PERIOD_HIGH 0x0 37 #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) 38 39 /* 40 * PLL configuration 41 */ 42 43 #define CONFIG_SYS_DA850_PLL0_PLLM \ 44 ((calimain_get_osc_freq() == 25000000) ? 23 : 24) 45 #define CONFIG_SYS_DA850_PLL1_PLLM \ 46 ((calimain_get_osc_freq() == 25000000) ? 20 : 21) 47 48 /* 49 * DDR2 memory configuration 50 */ 51 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 52 DV_DDR_PHY_EXT_STRBEN | \ 53 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 54 55 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 56 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ 57 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \ 58 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 59 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 60 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 61 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 62 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \ 63 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 64 65 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 66 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 67 68 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 69 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 70 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ 71 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 72 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 73 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 74 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \ 75 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 76 (1 << DV_DDR_SDTMR1_WTR_SHIFT)) 77 78 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 79 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 80 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ 81 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 82 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 83 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 84 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 85 (2 << DV_DDR_SDTMR2_CKE_SHIFT)) 86 87 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF 88 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 89 90 /* 91 * Flash memory timing 92 */ 93 94 #define CONFIG_SYS_DA850_CS2CFG ( \ 95 DAVINCI_ABCR_WSETUP(2) | \ 96 DAVINCI_ABCR_WSTROBE(5) | \ 97 DAVINCI_ABCR_WHOLD(3) | \ 98 DAVINCI_ABCR_RSETUP(1) | \ 99 DAVINCI_ABCR_RSTROBE(14) | \ 100 DAVINCI_ABCR_RHOLD(0) | \ 101 DAVINCI_ABCR_TA(3) | \ 102 DAVINCI_ABCR_ASIZE_16BIT) 103 104 /* single 64 MB NOR flash device connected to CS2 and CS3 */ 105 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG 106 107 /* 108 * Memory Info 109 */ 110 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 111 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 112 #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ 113 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 114 115 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 116 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 117 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ 118 DAVINCI_SYSCFG_SUSPSRC_UART2 | \ 119 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 120 DAVINCI_SYSCFG_SUSPSRC_I2C) 121 122 /* memtest start addr */ 123 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 124 125 /* memtest will be run on 16MB */ 126 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20)) 127 128 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 129 130 /* 131 * Serial Driver info 132 */ 133 #define CONFIG_SYS_NS16550_SERIAL 134 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 135 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ 136 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 137 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 138 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_PROTECTION 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ 144 #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ 145 #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 146 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ 147 #define CONFIG_ENV_ADDR \ 148 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2) 149 #define CONFIG_ENV_SIZE (128 << 10) 150 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 151 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 152 #define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */ 153 #define CONFIG_SYS_MAX_FLASH_SECT \ 154 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3) 155 156 /* 157 * Network & Ethernet Configuration 158 */ 159 #ifdef CONFIG_DRIVER_TI_EMAC 160 #define CONFIG_MII 161 #define CONFIG_BOOTP_DNS 162 #define CONFIG_BOOTP_DNS2 163 #define CONFIG_BOOTP_SEND_HOSTNAME 164 #define CONFIG_NET_RETRY_COUNT 10 165 #endif 166 167 /* 168 * U-Boot general configuration 169 */ 170 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 171 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 173 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 174 #define CONFIG_LOADADDR 0xc0700000 175 #define CONFIG_AUTO_COMPLETE 176 #define CONFIG_CMDLINE_EDITING 177 #define CONFIG_SYS_LONGHELP 178 #define CONFIG_MX_CYCLIC 179 180 /* 181 * Linux Information 182 */ 183 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 184 #define CONFIG_CMDLINE_TAG 185 #define CONFIG_REVISION_TAG 186 #define CONFIG_SETUP_MEMORY_TAGS 187 #define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;" 188 #define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */ 189 #define CONFIG_RESET_TO_RETRY 190 191 /* 192 * Default environment settings 193 * gpio0 = button, gpio1 = led green, gpio2 = led red 194 * verify = n ... disable kernel checksum verification for faster booting 195 */ 196 #define CONFIG_EXTRA_ENV_SETTINGS \ 197 "tftpdir=calimero\0" \ 198 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \ 199 "erase 0x60800000 +0x400000; " \ 200 "cp.b $loadaddr 0x60800000 $filesize\0" \ 201 "flashrootfs=" \ 202 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \ 203 "erase 0x60c00000 +0x2e00000; " \ 204 "cp.b $loadaddr 0x60c00000 $filesize\0" \ 205 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \ 206 "protect off all; " \ 207 "erase 0x60000000 +0x80000; " \ 208 "cp.b $loadaddr 0x60000000 $filesize\0" \ 209 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \ 210 "erase 0x60080000 +0x780000; " \ 211 "cp.b $loadaddr 0x60080000 $filesize\0" \ 212 "erase_persistent=erase 0x63a00000 +0x600000;\0" \ 213 "bootnor=setenv bootargs console=ttyS2,115200n8 " \ 214 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 215 "rootwait ethaddr=$ethaddr; " \ 216 "gpio c 1; gpio s 2; bootm 0x60800000\0" \ 217 "bootrlk=gpio s 1; gpio s 2;" \ 218 "setenv bootargs console=ttyS2,115200n8 " \ 219 "ethaddr=$ethaddr; bootm 0x60080000\0" \ 220 "boottftp=setenv bootargs console=ttyS2,115200n8 " \ 221 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \ 222 "rootwait ethaddr=$ethaddr; " \ 223 "tftpboot $loadaddr $tftpdir/uImage;" \ 224 "gpio c 1; gpio s 2; bootm $loadaddr\0" \ 225 "checkupdate=if test -n $update_flag; then " \ 226 "echo Previous update failed - starting RLK; " \ 227 "run bootrlk; fi; " \ 228 "if test -n $initial_setup; then " \ 229 "echo Running initial setup procedure; " \ 230 "sleep 1; run flashall; fi\0" \ 231 "product=accessory\0" \ 232 "serial=XX12345\0" \ 233 "checknor=" \ 234 "if gpio i 0; then run bootnor; fi;\0" \ 235 "checkrlk=" \ 236 "if gpio i 0; then run bootrlk; fi;\0" \ 237 "checkbutton=" \ 238 "run checknor; sleep 1;" \ 239 "run checknor; sleep 1;" \ 240 "run checknor; sleep 1;" \ 241 "run checknor; sleep 1;" \ 242 "run checknor;" \ 243 "gpio s 1; gpio s 2;" \ 244 "echo ---- Release button to boot RLK ----;" \ 245 "run checkrlk; sleep 1;" \ 246 "run checkrlk; sleep 1;" \ 247 "run checkrlk; sleep 1;" \ 248 "run checkrlk; sleep 1;" \ 249 "run checkrlk; sleep 1;" \ 250 "run checkrlk;" \ 251 "echo ---- Factory reset requested ----;" \ 252 "gpio c 1;" \ 253 "setenv factory_reset true;" \ 254 "saveenv;" \ 255 "run bootnor;\0" \ 256 "flashall=run flashrlk;" \ 257 "run flashkernel;" \ 258 "run flashrootfs;" \ 259 "setenv erase_datafs true;" \ 260 "setenv initial_setup;" \ 261 "saveenv;" \ 262 "run bootnor;\0" \ 263 "verify=n\0" \ 264 "clearenv=protect off all;" \ 265 "erase 0x60040000 +0x40000;\0" \ 266 "bootlimit=3\0" \ 267 "altbootcmd=run bootrlk\0" 268 269 #define CONFIG_PREBOOT \ 270 "echo Version: $ver; " \ 271 "echo Serial: $serial; " \ 272 "echo MAC: $ethaddr; " \ 273 "echo Product: $product; " \ 274 "gpio c 1; gpio c 2;" 275 276 /* additions for new relocation code, must added to all boards */ 277 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 278 /* initial stack pointer in internal SRAM */ 279 #define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00) 280 281 #define CONFIG_BOOTCOUNT_LIMIT 282 #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ 283 #define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE 284 285 #ifndef __ASSEMBLY__ 286 int calimain_get_osc_freq(void); 287 #endif 288 289 #include <asm/arch/hardware.h> 290 291 #endif /* __CONFIG_H */ 292