xref: /openbmc/u-boot/include/configs/calimain.h (revision 3ba98ed8)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011-2014 OMICRON electronics GmbH
4  *
5  * Based on da850evm.h. Original Copyrights follow:
6  *
7  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * Board
16  */
17 #define CONFIG_MACH_TYPE	MACH_TYPE_CALIMAIN
18 
19 /*
20  * SoC Configuration
21  */
22 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
23 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
24 #define CONFIG_SYS_OSCIN_FREQ		calimain_get_osc_freq()
25 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
26 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
27 #define CONFIG_ARCH_CPU_INIT
28 #define CONFIG_HW_WATCHDOG
29 #define CONFIG_SYS_WDTTIMERBASE	DAVINCI_TIMER1_BASE
30 #define CONFIG_SYS_WDT_PERIOD_LOW \
31 	(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
32 #define CONFIG_SYS_WDT_PERIOD_HIGH	0x0
33 #define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
34 
35 /*
36  * PLL configuration
37  */
38 
39 #define CONFIG_SYS_DA850_PLL0_PLLM \
40 	((calimain_get_osc_freq() == 25000000) ? 23 : 24)
41 #define CONFIG_SYS_DA850_PLL1_PLLM \
42 	((calimain_get_osc_freq() == 25000000) ? 20 : 21)
43 
44 /*
45  * DDR2 memory configuration
46  */
47 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
48 					DV_DDR_PHY_EXT_STRBEN | \
49 					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
50 
51 #define CONFIG_SYS_DA850_DDR2_SDBCR (		\
52 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
53 	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
54 	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
55 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
56 	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
57 	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
58 	(0x3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
59 	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
60 
61 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
62 #define CONFIG_SYS_DA850_DDR2_SDBCR2	0
63 
64 #define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
65 	(16 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
66 	(1 << DV_DDR_SDTMR1_RP_SHIFT) |		\
67 	(1 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
68 	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
69 	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
70 	(7 << DV_DDR_SDTMR1_RC_SHIFT) |		\
71 	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
72 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
73 
74 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
75 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
76 	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
77 	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
78 	(18 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
79 	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
80 	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
81 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
82 
83 #define CONFIG_SYS_DA850_DDR2_SDRCR	0x000003FF
84 #define CONFIG_SYS_DA850_DDR2_PBBPR	0x30
85 
86 /*
87  * Flash memory timing
88  */
89 
90 #define CONFIG_SYS_DA850_CS2CFG	(	\
91 	DAVINCI_ABCR_WSETUP(2) |	\
92 	DAVINCI_ABCR_WSTROBE(5)	|	\
93 	DAVINCI_ABCR_WHOLD(3) |		\
94 	DAVINCI_ABCR_RSETUP(1) |	\
95 	DAVINCI_ABCR_RSTROBE(14) |	\
96 	DAVINCI_ABCR_RHOLD(0) |		\
97 	DAVINCI_ABCR_TA(3) |		\
98 	DAVINCI_ABCR_ASIZE_16BIT)
99 
100 /* single 64 MB NOR flash device connected to CS2 and CS3 */
101 #define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
102 
103 /*
104  * Memory Info
105  */
106 #define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
107 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
108 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
109 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
110 
111 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
112 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
113 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
114 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
115 	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
116 	DAVINCI_SYSCFG_SUSPSRC_I2C)
117 
118 /* memtest start addr */
119 #define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
120 
121 /* memtest will be run on 16MB */
122 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (16 << 20))
123 
124 /*
125  * Serial Driver info
126  */
127 #define CONFIG_SYS_NS16550_SERIAL
128 #define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
129 #define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
130 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
131 
132 #define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
133 #define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
134 #define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
135 #define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
136 #define CONFIG_ENV_ADDR \
137 	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
138 #define CONFIG_ENV_SIZE             (128 << 10)
139 #define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
140 #define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
141 #define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
142 #define CONFIG_SYS_MAX_FLASH_SECT \
143 	((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
144 
145 /*
146  * Network & Ethernet Configuration
147  */
148 #ifdef CONFIG_DRIVER_TI_EMAC
149 #define CONFIG_BOOTP_DNS2
150 #define CONFIG_BOOTP_SEND_HOSTNAME
151 #define CONFIG_NET_RETRY_COUNT	10
152 #endif
153 
154 /*
155  * U-Boot general configuration
156  */
157 #define CONFIG_BOOTFILE        "uImage" /* Boot file name */
158 #define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size	*/
159 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
160 #define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
161 #define CONFIG_LOADADDR        0xc0700000
162 #define CONFIG_MX_CYCLIC
163 
164 /*
165  * Linux Information
166  */
167 #define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
168 #define CONFIG_CMDLINE_TAG
169 #define CONFIG_REVISION_TAG
170 #define CONFIG_SETUP_MEMORY_TAGS
171 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
172 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
173 #define CONFIG_RESET_TO_RETRY
174 
175 /*
176  * Default environment settings
177  * gpio0 = button, gpio1 = led green, gpio2 = led red
178  * verify = n ... disable kernel checksum verification for faster booting
179  */
180 #define CONFIG_EXTRA_ENV_SETTINGS					\
181 	"tftpdir=calimero\0"						\
182 	"flashkernel=tftpboot $loadaddr $tftpdir/uImage; "		\
183 		"erase 0x60800000 +0x400000; "				\
184 		"cp.b $loadaddr 0x60800000 $filesize\0"			\
185 	"flashrootfs="							\
186 		"tftpboot $loadaddr $tftpdir/rootfs.jffs2; "		\
187 		"erase 0x60c00000 +0x2e00000; "				\
188 		"cp.b $loadaddr 0x60c00000 $filesize\0"			\
189 	"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "		\
190 		"protect off all; "					\
191 		"erase 0x60000000 +0x80000; "				\
192 		"cp.b $loadaddr 0x60000000 $filesize\0"			\
193 	"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "		\
194 		"erase 0x60080000 +0x780000; "				\
195 		"cp.b $loadaddr 0x60080000 $filesize\0"			\
196 	"erase_persistent=erase 0x63a00000 +0x600000;\0"		\
197 	"bootnor=setenv bootargs console=ttyS2,115200n8 "		\
198 		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
199 		"rootwait ethaddr=$ethaddr; "				\
200 		"gpio c 1; gpio s 2; bootm 0x60800000\0"		\
201 	"bootrlk=gpio s 1; gpio s 2;"					\
202 		"setenv bootargs console=ttyS2,115200n8 "		\
203 		"ethaddr=$ethaddr; bootm 0x60080000\0"			\
204 	"boottftp=setenv bootargs console=ttyS2,115200n8 "		\
205 		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
206 		"rootwait ethaddr=$ethaddr; "				\
207 		"tftpboot $loadaddr $tftpdir/uImage;"			\
208 		"gpio c 1; gpio s 2; bootm $loadaddr\0"			\
209 	"checkupdate=if test -n $update_flag; then "			\
210 		"echo Previous update failed - starting RLK; "		\
211 		"run bootrlk; fi; "					\
212 		"if test -n $initial_setup; then "			\
213 		"echo Running initial setup procedure; "		\
214 		"sleep 1; run flashall; fi\0"				\
215 	"product=accessory\0"						\
216 	"serial=XX12345\0"						\
217 	"checknor="							\
218 		"if gpio i 0; then run bootnor; fi;\0"			\
219 	"checkrlk="							\
220 		"if gpio i 0; then run bootrlk; fi;\0"			\
221 	"checkbutton="							\
222 		"run checknor; sleep 1;"				\
223 		"run checknor; sleep 1;"				\
224 		"run checknor; sleep 1;"				\
225 		"run checknor; sleep 1;"				\
226 		"run checknor;"						\
227 		"gpio s 1; gpio s 2;"					\
228 		"echo ---- Release button to boot RLK ----;"		\
229 		"run checkrlk; sleep 1;"				\
230 		"run checkrlk; sleep 1;"				\
231 		"run checkrlk; sleep 1;"				\
232 		"run checkrlk; sleep 1;"				\
233 		"run checkrlk; sleep 1;"				\
234 		"run checkrlk;"						\
235 		"echo ---- Factory reset requested ----;"		\
236 		"gpio c 1;"						\
237 		"setenv factory_reset true;"				\
238 		"saveenv;"						\
239 		"run bootnor;\0"					\
240 	"flashall=run flashrlk;"					\
241 		"run flashkernel;"					\
242 		"run flashrootfs;"					\
243 		"setenv erase_datafs true;"				\
244 		"setenv initial_setup;"					\
245 		"saveenv;"						\
246 		"run bootnor;\0"					\
247 	"verify=n\0"							\
248 	"clearenv=protect off all;"					\
249 		"erase 0x60040000 +0x40000;\0"				\
250 	"altbootcmd=run bootrlk\0"
251 
252 #define CONFIG_PREBOOT			\
253 	"echo Version: $ver; "		\
254 	"echo Serial: $serial; "	\
255 	"echo MAC: $ethaddr; "		\
256 	"echo Product: $product; "	\
257 	"gpio c 1; gpio c 2;"
258 
259 /* additions for new relocation code, must added to all boards */
260 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
261 /* initial stack pointer in internal SRAM */
262 #define CONFIG_SYS_INIT_SP_ADDR		(0x8001ff00)
263 
264 #define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
265 
266 #ifndef __ASSEMBLY__
267 int calimain_get_osc_freq(void);
268 #endif
269 
270 #include <asm/arch/hardware.h>
271 
272 #endif /* __CONFIG_H */
273