1*341032d3SPhilippe Reynes /* SPDX-License-Identifier: GPL-2.0+ */ 2*341032d3SPhilippe Reynes /* 3*341032d3SPhilippe Reynes * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> 4*341032d3SPhilippe Reynes */ 5*341032d3SPhilippe Reynes 6*341032d3SPhilippe Reynes #ifndef __CONFIG_BMIPS_BCM6838_H 7*341032d3SPhilippe Reynes #define __CONFIG_BMIPS_BCM6838_H 8*341032d3SPhilippe Reynes 9*341032d3SPhilippe Reynes /* CPU */ 10*341032d3SPhilippe Reynes #define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 11*341032d3SPhilippe Reynes 12*341032d3SPhilippe Reynes /* RAM */ 13*341032d3SPhilippe Reynes #define CONFIG_SYS_SDRAM_BASE 0x80000000 14*341032d3SPhilippe Reynes 15*341032d3SPhilippe Reynes /* U-Boot */ 16*341032d3SPhilippe Reynes #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 17*341032d3SPhilippe Reynes 18*341032d3SPhilippe Reynes #if defined(CONFIG_BMIPS_BOOT_RAM) 19*341032d3SPhilippe Reynes #define CONFIG_SKIP_LOWLEVEL_INIT 20*341032d3SPhilippe Reynes #define CONFIG_SYS_INIT_SP_OFFSET 0x2000 21*341032d3SPhilippe Reynes #endif 22*341032d3SPhilippe Reynes 23*341032d3SPhilippe Reynes #endif /* __CONFIG_BMIPS_BCM6838_H */ 24