1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. 4 */ 5 6 #ifndef _CONFIG_AXS10X_H_ 7 #define _CONFIG_AXS10X_H_ 8 9 #include <linux/sizes.h> 10 /* 11 * CPU configuration 12 */ 13 #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 14 #define ARC_APB_PERIPHERAL_BASE 0xF0000000 15 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) 16 #define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) 17 18 /* 19 * Memory configuration 20 */ 21 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 22 23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 25 #define CONFIG_SYS_SDRAM_SIZE SZ_512M 26 27 #define CONFIG_SYS_INIT_SP_ADDR \ 28 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 29 30 #define CONFIG_SYS_MALLOC_LEN SZ_2M 31 #define CONFIG_SYS_BOOTM_LEN SZ_128M 32 #define CONFIG_SYS_LOAD_ADDR 0x82000000 33 34 /* 35 * This board might be of different versions so handle it 36 */ 37 #define CONFIG_BOARD_TYPES 38 39 /* 40 * NAND Flash configuration 41 */ 42 #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 45 /* 46 * UART configuration 47 */ 48 #define CONFIG_DW_SERIAL 49 #define CONFIG_SYS_NS16550_SERIAL 50 #define CONFIG_SYS_NS16550_CLK 33333333 51 #define CONFIG_SYS_NS16550_MEM32 52 53 /* 54 * Ethernet PHY configuration 55 */ 56 #define CONFIG_MII 57 58 /* 59 * USB 1.1 configuration 60 */ 61 #define CONFIG_USB_OHCI_NEW 62 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 63 64 /* 65 * Environment settings 66 */ 67 #define CONFIG_ENV_SIZE SZ_16K 68 69 /* 70 * Environment configuration 71 */ 72 #define CONFIG_BOOTFILE "uImage" 73 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 74 75 /* 76 * Console configuration 77 */ 78 79 /* 80 * Misc utility configuration 81 */ 82 #define CONFIG_BOUNCE_BUFFER 83 84 #endif /* _CONFIG_AXS10X_H_ */ 85