1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017 Andes Technology Corporation 4 * Rick Chen, Andes Technology Corporation <rick@andestech.com> 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * CPU and Board Configuration Options 12 */ 13 #define CONFIG_BOOTP_SEND_HOSTNAME 14 15 /* 16 * Miscellaneous configurable options 17 */ 18 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 19 20 /* 21 * Print Buffer Size 22 */ 23 #define CONFIG_SYS_PBSIZE \ 24 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 25 26 /* 27 * max number of command args 28 */ 29 #define CONFIG_SYS_MAXARGS 16 30 31 /* 32 * Boot Argument Buffer Size 33 */ 34 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 35 36 /* 37 * Size of malloc() pool 38 * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough 39 */ 40 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 41 42 /* DT blob (fdt) address */ 43 #define CONFIG_SYS_FDT_BASE 0x000f0000 44 45 /* 46 * Physical Memory Map 47 */ 48 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 49 #define PHYS_SDRAM_1 \ 50 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 51 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 52 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 53 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 54 55 /* 56 * Serial console configuration 57 */ 58 #define CONFIG_SYS_NS16550_SERIAL 59 #ifndef CONFIG_DM_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE -4 61 #endif 62 #define CONFIG_SYS_NS16550_CLK 19660800 63 64 /* Init Stack Pointer */ 65 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ 66 GENERATED_GBL_DATA_SIZE) 67 68 /* 69 * Load address and memory test area should agree with 70 * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. 71 */ 72 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ 73 74 /* 75 * memtest works on 512 MB in DRAM 76 */ 77 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 78 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) 79 80 /* 81 * FLASH and environment organization 82 */ 83 84 /* use CFI framework */ 85 #define CONFIG_SYS_FLASH_CFI 86 #define CONFIG_FLASH_CFI_DRIVER 87 88 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 89 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 90 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 91 92 /* support JEDEC */ 93 #ifdef CONFIG_CFI_FLASH 94 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 95 #endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 96 #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ 97 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 98 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 99 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 100 101 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 102 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 103 104 /* max number of memory banks */ 105 /* 106 * There are 4 banks supported for this Controller, 107 * but we have only 1 bank connected to flash on board 108 */ 109 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 110 #define CONFIG_SYS_MAX_FLASH_BANKS 1 111 #endif 112 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 113 114 /* max number of sectors on one chip */ 115 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 116 #define CONFIG_SYS_MAX_FLASH_SECT 512 117 118 /* environments */ 119 #define CONFIG_ENV_SPI_BUS 0 120 #define CONFIG_ENV_SPI_CS 0 121 #define CONFIG_ENV_SPI_MAX_HZ 50000000 122 #define CONFIG_ENV_SPI_MODE 0 123 #define CONFIG_ENV_SECT_SIZE 0x1000 124 #define CONFIG_ENV_OVERWRITE 125 126 /* SPI FLASH */ 127 #define CONFIG_SF_DEFAULT_BUS 0 128 #define CONFIG_SF_DEFAULT_CS 0 129 #define CONFIG_SF_DEFAULT_SPEED 1000000 130 #define CONFIG_SF_DEFAULT_MODE 0 131 132 /* 133 * For booting Linux, the board info and command line data 134 * have to be in the first 16 MB of memory, since this is 135 * the maximum mapped by the Linux kernel during initialization. 136 */ 137 138 /* Initial Memory map for Linux*/ 139 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 140 /* Increase max gunzip size */ 141 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 142 143 /* When we use RAM as ENV */ 144 #define CONFIG_ENV_SIZE 0x2000 145 146 /* Enable distro boot */ 147 #define BOOT_TARGET_DEVICES(func) \ 148 func(MMC, mmc, 0) \ 149 func(DHCP, dhcp, na) 150 #include <config_distro_bootcmd.h> 151 152 #define CONFIG_EXTRA_ENV_SETTINGS \ 153 "kernel_addr_r=0x00080000\0" \ 154 "pxefile_addr_r=0x01f00000\0" \ 155 "scriptaddr=0x01f00000\0" \ 156 "fdt_addr_r=0x02000000\0" \ 157 "ramdisk_addr_r=0x02800000\0" \ 158 BOOTENV 159 160 #endif /* __CONFIG_H */ 161