1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Atmel Corporation 4 * 5 * Configuation settings for the AT91SAM9X5EK board. 6 */ 7 8 #ifndef __CONFIG_H__ 9 #define __CONFIG_H__ 10 11 /* ARM asynchronous clock */ 12 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 13 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 14 15 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 16 #define CONFIG_SETUP_MEMORY_TAGS 17 #define CONFIG_INITRD_TAG 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 /* general purpose I/O */ 21 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 22 23 /* 24 * BOOTP options 25 */ 26 #define CONFIG_BOOTP_BOOTFILESIZE 27 28 /* 29 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) 30 * NB: in this case, USB 1.1 devices won't be recognized. 31 */ 32 33 /* SDRAM */ 34 #define CONFIG_SYS_SDRAM_BASE 0x20000000 35 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 36 37 #define CONFIG_SYS_INIT_SP_ADDR \ 38 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 39 40 /* DataFlash */ 41 #ifdef CONFIG_CMD_SF 42 #define CONFIG_SF_DEFAULT_SPEED 30000000 43 #endif 44 45 /* NAND flash */ 46 #ifdef CONFIG_CMD_NAND 47 #define CONFIG_SYS_MAX_NAND_DEVICE 1 48 #define CONFIG_SYS_NAND_BASE 0x40000000 49 #define CONFIG_SYS_NAND_DBW_8 1 50 /* our ALE is AD21 */ 51 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 52 /* our CLE is AD22 */ 53 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 54 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 55 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 56 #endif 57 58 /* USB */ 59 #ifdef CONFIG_CMD_USB 60 #ifndef CONFIG_USB_EHCI_HCD 61 #define CONFIG_USB_ATMEL 62 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 63 #define CONFIG_USB_OHCI_NEW 64 #define CONFIG_SYS_USB_OHCI_CPU_INIT 65 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 66 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" 67 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 68 #endif 69 #endif 70 71 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 72 73 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 74 #define CONFIG_SYS_MEMTEST_END 0x26e00000 75 76 #ifdef CONFIG_NAND_BOOT 77 /* bootstrap + u-boot + env + linux in nandflash */ 78 #define CONFIG_ENV_OFFSET 0x140000 79 #define CONFIG_ENV_OFFSET_REDUND 0x100000 80 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 81 #define CONFIG_BOOTCOMMAND "nand read " \ 82 "0x22000000 0x200000 0x600000; " \ 83 "nand read 0x21000000 0x180000 0x20000; " \ 84 "bootz 0x22000000 - 0x21000000" 85 #elif defined(CONFIG_SPI_BOOT) 86 /* bootstrap + u-boot + env + linux in spi flash */ 87 #define CONFIG_ENV_OFFSET 0x5000 88 #define CONFIG_ENV_SIZE 0x3000 89 #define CONFIG_ENV_SECT_SIZE 0x1000 90 #define CONFIG_ENV_SPI_MAX_HZ 30000000 91 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 92 "sf read 0x22000000 0x100000 0x300000; " \ 93 "bootm 0x22000000" 94 #elif defined(CONFIG_SYS_USE_DATAFLASH) 95 /* bootstrap + u-boot + env + linux in data flash */ 96 #define CONFIG_ENV_OFFSET 0x4200 97 #define CONFIG_ENV_SIZE 0x4200 98 #define CONFIG_ENV_SECT_SIZE 0x210 99 #define CONFIG_ENV_SPI_MAX_HZ 30000000 100 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 101 "sf read 0x22000000 0x84000 0x294000; " \ 102 "bootm 0x22000000" 103 #else /* CONFIG_SD_BOOT */ 104 /* bootstrap + u-boot + env + linux in mmc */ 105 #define CONFIG_ENV_SIZE 0x4000 106 #endif 107 108 /* 109 * Size of malloc() pool 110 */ 111 #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) 112 113 /* SPL */ 114 #define CONFIG_SPL_TEXT_BASE 0x300000 115 #define CONFIG_SPL_MAX_SIZE 0x6000 116 #define CONFIG_SPL_STACK 0x308000 117 118 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 119 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 120 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 121 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 122 123 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 124 125 #define CONFIG_SYS_MASTER_CLOCK 132096000 126 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 127 #define CONFIG_SYS_MCKR 0x1301 128 #define CONFIG_SYS_MCKR_CSS 0x1302 129 130 #ifdef CONFIG_SD_BOOT 131 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 132 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 133 134 #elif CONFIG_SPI_BOOT 135 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 136 137 #elif CONFIG_NAND_BOOT 138 #define CONFIG_SPL_NAND_DRIVERS 139 #define CONFIG_SPL_NAND_BASE 140 #endif 141 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 142 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 143 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 144 #define CONFIG_SYS_NAND_PAGE_COUNT 64 145 #define CONFIG_SYS_NAND_OOBSIZE 64 146 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 147 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 148 149 #endif 150