1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * Configuation settings for the AT91SAM9X5EK board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H__ 10 #define __CONFIG_H__ 11 12 #include <asm/hardware.h> 13 14 #define CONFIG_SYS_TEXT_BASE 0x26f00000 15 16 /* ARM asynchronous clock */ 17 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 18 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 19 20 #define CONFIG_AT91SAM9X5EK 21 22 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 23 #define CONFIG_SETUP_MEMORY_TAGS 24 #define CONFIG_INITRD_TAG 25 #define CONFIG_SKIP_LOWLEVEL_INIT 26 27 /* general purpose I/O */ 28 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 29 30 /* LCD */ 31 #define LCD_BPP LCD_COLOR16 32 #define LCD_OUTPUT_BPP 24 33 #define CONFIG_LCD_LOGO 34 #define CONFIG_LCD_INFO 35 #define CONFIG_LCD_INFO_BELOW_LOGO 36 #define CONFIG_ATMEL_HLCD 37 #define CONFIG_ATMEL_LCD_RGB565 38 39 40 /* 41 * BOOTP options 42 */ 43 #define CONFIG_BOOTP_BOOTFILESIZE 44 #define CONFIG_BOOTP_BOOTPATH 45 #define CONFIG_BOOTP_GATEWAY 46 #define CONFIG_BOOTP_HOSTNAME 47 48 /* 49 * Command line configuration. 50 */ 51 #define CONFIG_CMD_NAND 52 53 /* 54 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) 55 * NB: in this case, USB 1.1 devices won't be recognized. 56 */ 57 58 /* SDRAM */ 59 #define CONFIG_NR_DRAM_BANKS 1 60 #define CONFIG_SYS_SDRAM_BASE 0x20000000 61 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 62 63 #define CONFIG_SYS_INIT_SP_ADDR \ 64 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 65 66 /* DataFlash */ 67 #ifdef CONFIG_CMD_SF 68 #define CONFIG_SF_DEFAULT_SPEED 30000000 69 #endif 70 71 /* NAND flash */ 72 #ifdef CONFIG_CMD_NAND 73 #define CONFIG_NAND_ATMEL 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 75 #define CONFIG_SYS_NAND_BASE 0x40000000 76 #define CONFIG_SYS_NAND_DBW_8 1 77 /* our ALE is AD21 */ 78 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 79 /* our CLE is AD22 */ 80 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 81 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 82 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 83 84 /* PMECC & PMERRLOC */ 85 #define CONFIG_ATMEL_NAND_HWECC 1 86 #define CONFIG_ATMEL_NAND_HW_PMECC 1 87 #define CONFIG_PMECC_CAP 2 88 #define CONFIG_PMECC_SECTOR_SIZE 512 89 90 #define CONFIG_CMD_NAND_TRIMFFS 91 92 #define CONFIG_MTD_DEVICE 93 #define CONFIG_MTD_PARTITIONS 94 #endif 95 96 /* USB */ 97 #ifdef CONFIG_CMD_USB 98 #ifndef CONFIG_USB_EHCI_HCD 99 #define CONFIG_USB_ATMEL 100 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 101 #define CONFIG_USB_OHCI_NEW 102 #define CONFIG_SYS_USB_OHCI_CPU_INIT 103 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 104 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" 105 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 106 #endif 107 #endif 108 109 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 110 111 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 112 #define CONFIG_SYS_MEMTEST_END 0x26e00000 113 114 #ifdef CONFIG_SYS_USE_NANDFLASH 115 /* bootstrap + u-boot + env + linux in nandflash */ 116 #define CONFIG_ENV_OFFSET 0x120000 117 #define CONFIG_ENV_OFFSET_REDUND 0x100000 118 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 119 #define CONFIG_BOOTCOMMAND "nand read " \ 120 "0x22000000 0x200000 0x300000; " \ 121 "bootm 0x22000000" 122 #elif defined(CONFIG_SYS_USE_SPIFLASH) 123 /* bootstrap + u-boot + env + linux in spi flash */ 124 #define CONFIG_ENV_IS_IN_SPI_FLASH 125 #define CONFIG_ENV_OFFSET 0x5000 126 #define CONFIG_ENV_SIZE 0x3000 127 #define CONFIG_ENV_SECT_SIZE 0x1000 128 #define CONFIG_ENV_SPI_MAX_HZ 30000000 129 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 130 "sf read 0x22000000 0x100000 0x300000; " \ 131 "bootm 0x22000000" 132 #elif defined(CONFIG_SYS_USE_DATAFLASH) 133 /* bootstrap + u-boot + env + linux in data flash */ 134 #define CONFIG_ENV_IS_IN_SPI_FLASH 135 #define CONFIG_ENV_OFFSET 0x4200 136 #define CONFIG_ENV_SIZE 0x4200 137 #define CONFIG_ENV_SECT_SIZE 0x210 138 #define CONFIG_ENV_SPI_MAX_HZ 30000000 139 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 140 "sf read 0x22000000 0x84000 0x294000; " \ 141 "bootm 0x22000000" 142 #else /* CONFIG_SYS_USE_MMC */ 143 /* bootstrap + u-boot + env + linux in mmc */ 144 #define CONFIG_ENV_IS_IN_FAT 145 #define FAT_ENV_INTERFACE "mmc" 146 #define FAT_ENV_FILE "uboot.env" 147 #define FAT_ENV_DEVICE_AND_PART "0" 148 #define CONFIG_ENV_SIZE 0x4000 149 #endif 150 151 #ifdef CONFIG_SYS_USE_MMC 152 #define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \ 153 "mtdparts=atmel_nand:" \ 154 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ 155 "root=/dev/mmcblk0p2 " \ 156 "rw rootfstype=ext4 rootwait" 157 #else 158 #define CONFIG_BOOTARGS \ 159 "console=ttyS0,115200 earlyprintk " \ 160 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 161 "256k(env),256k(env_redundant),256k(spare)," \ 162 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 163 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw" 164 #endif 165 166 #define CONFIG_SYS_CBSIZE 256 167 #define CONFIG_SYS_MAXARGS 16 168 #define CONFIG_SYS_LONGHELP 169 #define CONFIG_CMDLINE_EDITING 170 #define CONFIG_AUTO_COMPLETE 171 172 /* 173 * Size of malloc() pool 174 */ 175 #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) 176 177 /* SPL */ 178 #define CONFIG_SPL_FRAMEWORK 179 #define CONFIG_SPL_TEXT_BASE 0x300000 180 #define CONFIG_SPL_MAX_SIZE 0x6000 181 #define CONFIG_SPL_STACK 0x308000 182 183 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 184 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 185 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 186 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 187 188 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 189 190 #define CONFIG_SYS_MASTER_CLOCK 132096000 191 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 192 #define CONFIG_SYS_MCKR 0x1301 193 #define CONFIG_SYS_MCKR_CSS 0x1302 194 195 #ifdef CONFIG_SYS_USE_MMC 196 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds 197 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 198 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 199 200 #elif CONFIG_SYS_USE_NANDFLASH 201 #define CONFIG_SPL_NAND_DRIVERS 202 #define CONFIG_SPL_NAND_BASE 203 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 204 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 205 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 206 #define CONFIG_SYS_NAND_PAGE_COUNT 64 207 #define CONFIG_SYS_NAND_OOBSIZE 64 208 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 210 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 211 212 #elif CONFIG_SYS_USE_SPIFLASH 213 #define CONFIG_SPL_SPI_LOAD 214 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 215 216 #endif 217 218 #endif 219