1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Atmel Corporation 4 * 5 * Configuation settings for the AT91SAM9X5EK board. 6 */ 7 8 #ifndef __CONFIG_H__ 9 #define __CONFIG_H__ 10 11 /* ARM asynchronous clock */ 12 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 13 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 14 15 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 16 #define CONFIG_SETUP_MEMORY_TAGS 17 #define CONFIG_INITRD_TAG 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 /* general purpose I/O */ 21 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 22 23 /* 24 * BOOTP options 25 */ 26 #define CONFIG_BOOTP_BOOTFILESIZE 27 28 /* 29 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) 30 * NB: in this case, USB 1.1 devices won't be recognized. 31 */ 32 33 /* SDRAM */ 34 #define CONFIG_SYS_SDRAM_BASE 0x20000000 35 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 36 37 #define CONFIG_SYS_INIT_SP_ADDR \ 38 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 39 40 /* DataFlash */ 41 42 /* NAND flash */ 43 #ifdef CONFIG_CMD_NAND 44 #define CONFIG_SYS_MAX_NAND_DEVICE 1 45 #define CONFIG_SYS_NAND_BASE 0x40000000 46 #define CONFIG_SYS_NAND_DBW_8 1 47 /* our ALE is AD21 */ 48 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 49 /* our CLE is AD22 */ 50 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 51 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 52 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 53 #endif 54 55 /* USB */ 56 #ifdef CONFIG_CMD_USB 57 #ifndef CONFIG_USB_EHCI_HCD 58 #define CONFIG_USB_ATMEL 59 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 60 #define CONFIG_USB_OHCI_NEW 61 #define CONFIG_SYS_USB_OHCI_CPU_INIT 62 #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 63 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" 64 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 65 #endif 66 #endif 67 68 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 69 70 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 71 #define CONFIG_SYS_MEMTEST_END 0x26e00000 72 73 #ifdef CONFIG_NAND_BOOT 74 /* bootstrap + u-boot + env + linux in nandflash */ 75 #define CONFIG_ENV_OFFSET 0x140000 76 #define CONFIG_ENV_OFFSET_REDUND 0x100000 77 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 78 #define CONFIG_BOOTCOMMAND "nand read " \ 79 "0x22000000 0x200000 0x600000; " \ 80 "nand read 0x21000000 0x180000 0x20000; " \ 81 "bootz 0x22000000 - 0x21000000" 82 #elif defined(CONFIG_SPI_BOOT) 83 /* bootstrap + u-boot + env + linux in spi flash */ 84 #define CONFIG_ENV_OFFSET 0x5000 85 #define CONFIG_ENV_SIZE 0x3000 86 #define CONFIG_ENV_SECT_SIZE 0x1000 87 #define CONFIG_ENV_SPI_MAX_HZ 30000000 88 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 89 "sf read 0x22000000 0x100000 0x300000; " \ 90 "bootm 0x22000000" 91 #elif defined(CONFIG_SYS_USE_DATAFLASH) 92 /* bootstrap + u-boot + env + linux in data flash */ 93 #define CONFIG_ENV_OFFSET 0x4200 94 #define CONFIG_ENV_SIZE 0x4200 95 #define CONFIG_ENV_SECT_SIZE 0x210 96 #define CONFIG_ENV_SPI_MAX_HZ 30000000 97 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 98 "sf read 0x22000000 0x84000 0x294000; " \ 99 "bootm 0x22000000" 100 #else /* CONFIG_SD_BOOT */ 101 /* bootstrap + u-boot + env + linux in mmc */ 102 #define CONFIG_ENV_SIZE 0x4000 103 #endif 104 105 /* 106 * Size of malloc() pool 107 */ 108 #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) 109 110 /* SPL */ 111 #define CONFIG_SPL_TEXT_BASE 0x300000 112 #define CONFIG_SPL_MAX_SIZE 0x6000 113 #define CONFIG_SPL_STACK 0x308000 114 115 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 116 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 117 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 118 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 119 120 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 121 122 #define CONFIG_SYS_MASTER_CLOCK 132096000 123 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 124 #define CONFIG_SYS_MCKR 0x1301 125 #define CONFIG_SYS_MCKR_CSS 0x1302 126 127 #ifdef CONFIG_SD_BOOT 128 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 129 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 130 131 #elif CONFIG_SPI_BOOT 132 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 133 134 #elif CONFIG_NAND_BOOT 135 #define CONFIG_SPL_NAND_DRIVERS 136 #define CONFIG_SPL_NAND_BASE 137 #endif 138 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 139 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 140 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 141 #define CONFIG_SYS_NAND_PAGE_COUNT 64 142 #define CONFIG_SYS_NAND_OOBSIZE 64 143 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 144 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 145 146 #endif 147