1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/hardware.h> 15 16 #define CONFIG_SYS_TEXT_BASE 0x73f00000 17 18 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 19 20 /* ARM asynchronous clock */ 21 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 22 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 23 24 #define CONFIG_AT91SAM9M10G45EK 25 26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 #define CONFIG_SKIP_LOWLEVEL_INIT 30 31 /* general purpose I/O */ 32 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 33 34 /* LCD */ 35 #define LCD_BPP LCD_COLOR8 36 #define CONFIG_LCD_LOGO 37 #undef LCD_TEST_PATTERN 38 #define CONFIG_LCD_INFO 39 #define CONFIG_LCD_INFO_BELOW_LOGO 40 #define CONFIG_ATMEL_LCD 41 #define CONFIG_ATMEL_LCD_RGB565 42 /* board specific(not enough SRAM) */ 43 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 44 45 /* 46 * BOOTP options 47 */ 48 #define CONFIG_BOOTP_BOOTFILESIZE 49 #define CONFIG_BOOTP_BOOTPATH 50 #define CONFIG_BOOTP_GATEWAY 51 #define CONFIG_BOOTP_HOSTNAME 52 53 /* SDRAM */ 54 #define CONFIG_NR_DRAM_BANKS 1 55 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 56 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 57 58 #define CONFIG_SYS_INIT_SP_ADDR \ 59 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 60 61 /* NAND flash */ 62 #ifdef CONFIG_CMD_NAND 63 #define CONFIG_NAND_ATMEL 64 #define CONFIG_SYS_MAX_NAND_DEVICE 1 65 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 66 #define CONFIG_SYS_NAND_DBW_8 67 /* our ALE is AD21 */ 68 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 69 /* our CLE is AD22 */ 70 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 71 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 72 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 73 74 #endif 75 76 /* Ethernet */ 77 #define CONFIG_RESET_PHY_R 78 #define CONFIG_AT91_WANTS_COMMON_PHY 79 80 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 81 82 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 83 #define CONFIG_SYS_MEMTEST_END 0x23e00000 84 85 #ifdef CONFIG_SYS_USE_NANDFLASH 86 /* bootstrap + u-boot + env in nandflash */ 87 #define CONFIG_ENV_OFFSET 0x120000 88 #define CONFIG_ENV_OFFSET_REDUND 0x100000 89 #define CONFIG_ENV_SIZE 0x20000 90 91 #define CONFIG_BOOTCOMMAND \ 92 "nand read 0x70000000 0x200000 0x300000;" \ 93 "bootm 0x70000000" 94 #elif CONFIG_SYS_USE_MMC 95 /* bootstrap + u-boot + env + linux in mmc */ 96 #define CONFIG_ENV_SIZE 0x4000 97 98 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ 99 "fatload mmc 0:1 0x72000000 zImage; " \ 100 "bootz 0x72000000 - 0x71000000" 101 #endif 102 103 #define CONFIG_SYS_CBSIZE 256 104 #define CONFIG_SYS_MAXARGS 16 105 #define CONFIG_SYS_LONGHELP 106 #define CONFIG_CMDLINE_EDITING 107 #define CONFIG_AUTO_COMPLETE 108 109 /* 110 * Size of malloc() pool 111 */ 112 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 113 114 /* Defines for SPL */ 115 #define CONFIG_SPL_FRAMEWORK 116 #define CONFIG_SPL_TEXT_BASE 0x300000 117 #define CONFIG_SPL_MAX_SIZE 0x010000 118 #define CONFIG_SPL_STACK 0x310000 119 120 #define CONFIG_SYS_MONITOR_LEN 0x80000 121 122 #ifdef CONFIG_SYS_USE_MMC 123 124 #define CONFIG_SPL_BSS_START_ADDR 0x70000000 125 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 126 #define CONFIG_SYS_SPL_MALLOC_START 0x70080000 127 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 128 129 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 130 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 131 132 #elif CONFIG_SYS_USE_NANDFLASH 133 #define CONFIG_SPL_NAND_DRIVERS 134 #define CONFIG_SPL_NAND_BASE 135 #define CONFIG_SPL_NAND_ECC 136 #define CONFIG_SPL_NAND_SOFTECC 137 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 138 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 139 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 140 141 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 142 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 143 #define CONFIG_SYS_NAND_PAGE_COUNT 64 144 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 145 #define CONFIG_SYS_NAND_ECCSIZE 256 146 #define CONFIG_SYS_NAND_ECCBYTES 3 147 #define CONFIG_SYS_NAND_OOBSIZE 64 148 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 149 48, 49, 50, 51, 52, 53, 54, 55, \ 150 56, 57, 58, 59, 60, 61, 62, 63, } 151 #endif 152 153 #define CONFIG_SPL_ATMEL_SIZE 154 #define CONFIG_SYS_MASTER_CLOCK 132096000 155 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 156 #define CONFIG_SYS_MCKR 0x1301 157 #define CONFIG_SYS_MCKR_CSS 0x1302 158 159 #endif 160