1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_TEXT_BASE 0x73f00000 15 16 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 17 18 /* ARM asynchronous clock */ 19 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 20 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 21 22 #define CONFIG_AT91SAM9M10G45EK 23 24 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 25 #define CONFIG_SETUP_MEMORY_TAGS 26 #define CONFIG_INITRD_TAG 27 #define CONFIG_SKIP_LOWLEVEL_INIT 28 29 /* general purpose I/O */ 30 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 31 32 /* LCD */ 33 #define LCD_BPP LCD_COLOR8 34 #define CONFIG_LCD_LOGO 35 #undef LCD_TEST_PATTERN 36 #define CONFIG_LCD_INFO 37 #define CONFIG_LCD_INFO_BELOW_LOGO 38 #define CONFIG_ATMEL_LCD 39 #define CONFIG_ATMEL_LCD_RGB565 40 /* board specific(not enough SRAM) */ 41 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 42 43 /* 44 * BOOTP options 45 */ 46 #define CONFIG_BOOTP_BOOTFILESIZE 47 #define CONFIG_BOOTP_BOOTPATH 48 #define CONFIG_BOOTP_GATEWAY 49 #define CONFIG_BOOTP_HOSTNAME 50 51 /* SDRAM */ 52 #define CONFIG_NR_DRAM_BANKS 1 53 #define CONFIG_SYS_SDRAM_BASE 0x70000000 54 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 55 56 #define CONFIG_SYS_INIT_SP_ADDR \ 57 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 58 59 /* NAND flash */ 60 #ifdef CONFIG_CMD_NAND 61 #define CONFIG_NAND_ATMEL 62 #define CONFIG_SYS_MAX_NAND_DEVICE 1 63 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 64 #define CONFIG_SYS_NAND_DBW_8 65 /* our ALE is AD21 */ 66 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 67 /* our CLE is AD22 */ 68 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 69 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 70 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 71 72 #endif 73 74 /* Ethernet */ 75 #define CONFIG_RESET_PHY_R 76 #define CONFIG_AT91_WANTS_COMMON_PHY 77 78 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 79 80 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 81 #define CONFIG_SYS_MEMTEST_END 0x23e00000 82 83 #ifdef CONFIG_NAND_BOOT 84 /* bootstrap + u-boot + env in nandflash */ 85 #define CONFIG_ENV_OFFSET 0x120000 86 #define CONFIG_ENV_OFFSET_REDUND 0x100000 87 #define CONFIG_ENV_SIZE 0x20000 88 89 #define CONFIG_BOOTCOMMAND \ 90 "nand read 0x70000000 0x200000 0x300000;" \ 91 "bootm 0x70000000" 92 #elif CONFIG_SD_BOOT 93 /* bootstrap + u-boot + env + linux in mmc */ 94 #define CONFIG_ENV_SIZE 0x4000 95 96 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ 97 "fatload mmc 0:1 0x72000000 zImage; " \ 98 "bootz 0x72000000 - 0x71000000" 99 #endif 100 101 #define CONFIG_SYS_LONGHELP 102 #define CONFIG_CMDLINE_EDITING 103 #define CONFIG_AUTO_COMPLETE 104 105 /* 106 * Size of malloc() pool 107 */ 108 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 109 110 /* Defines for SPL */ 111 #define CONFIG_SPL_FRAMEWORK 112 #define CONFIG_SPL_TEXT_BASE 0x300000 113 #define CONFIG_SPL_MAX_SIZE 0x010000 114 #define CONFIG_SPL_STACK 0x310000 115 116 #define CONFIG_SYS_MONITOR_LEN 0x80000 117 118 #ifdef CONFIG_SD_BOOT 119 120 #define CONFIG_SPL_BSS_START_ADDR 0x70000000 121 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 122 #define CONFIG_SYS_SPL_MALLOC_START 0x70080000 123 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 124 125 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 126 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 127 128 #elif CONFIG_NAND_BOOT 129 #define CONFIG_SPL_NAND_DRIVERS 130 #define CONFIG_SPL_NAND_BASE 131 #define CONFIG_SPL_NAND_ECC 132 #define CONFIG_SPL_NAND_SOFTECC 133 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 134 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 135 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 136 137 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 138 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 139 #define CONFIG_SYS_NAND_PAGE_COUNT 64 140 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 141 #define CONFIG_SYS_NAND_ECCSIZE 256 142 #define CONFIG_SYS_NAND_ECCBYTES 3 143 #define CONFIG_SYS_NAND_OOBSIZE 64 144 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 145 48, 49, 50, 51, 52, 53, 54, 55, \ 146 56, 57, 58, 59, 60, 61, 62, 63, } 147 #endif 148 149 #define CONFIG_SPL_ATMEL_SIZE 150 #define CONFIG_SYS_MASTER_CLOCK 132096000 151 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 152 #define CONFIG_SYS_MCKR 0x1301 153 #define CONFIG_SYS_MCKR_CSS 0x1302 154 155 #endif 156