1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
15 
16 /* ARM asynchronous clock */
17 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
18 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
19 
20 #define CONFIG_AT91SAM9M10G45EK
21 
22 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
23 #define CONFIG_SETUP_MEMORY_TAGS
24 #define CONFIG_INITRD_TAG
25 #define CONFIG_SKIP_LOWLEVEL_INIT
26 
27 /* general purpose I/O */
28 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
29 
30 /* LCD */
31 #define LCD_BPP				LCD_COLOR8
32 #define CONFIG_LCD_LOGO
33 #undef LCD_TEST_PATTERN
34 #define CONFIG_LCD_INFO
35 #define CONFIG_LCD_INFO_BELOW_LOGO
36 #define CONFIG_ATMEL_LCD
37 #define CONFIG_ATMEL_LCD_RGB565
38 /* board specific(not enough SRAM) */
39 #define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
40 
41 /*
42  * BOOTP options
43  */
44 #define CONFIG_BOOTP_BOOTFILESIZE
45 
46 /* SDRAM */
47 #define CONFIG_NR_DRAM_BANKS		1
48 #define CONFIG_SYS_SDRAM_BASE           0x70000000
49 #define CONFIG_SYS_SDRAM_SIZE		0x08000000
50 
51 #define CONFIG_SYS_INIT_SP_ADDR \
52 	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
53 
54 /* NAND flash */
55 #ifdef CONFIG_CMD_NAND
56 #define CONFIG_NAND_ATMEL
57 #define CONFIG_SYS_MAX_NAND_DEVICE		1
58 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
59 #define CONFIG_SYS_NAND_DBW_8
60 /* our ALE is AD21 */
61 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
62 /* our CLE is AD22 */
63 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
64 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
65 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
66 
67 #endif
68 
69 /* Ethernet */
70 #define CONFIG_RESET_PHY_R
71 #define CONFIG_AT91_WANTS_COMMON_PHY
72 
73 #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
74 
75 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
76 #define CONFIG_SYS_MEMTEST_END		0x23e00000
77 
78 #ifdef CONFIG_NAND_BOOT
79 /* bootstrap + u-boot + env in nandflash */
80 #define CONFIG_ENV_OFFSET		0x120000
81 #define CONFIG_ENV_OFFSET_REDUND	0x100000
82 #define CONFIG_ENV_SIZE			0x20000
83 
84 #define CONFIG_BOOTCOMMAND						\
85 	"nand read 0x70000000 0x200000 0x300000;"			\
86 	"bootm 0x70000000"
87 #elif CONFIG_SD_BOOT
88 /* bootstrap + u-boot + env + linux in mmc */
89 #define CONFIG_ENV_SIZE		0x4000
90 
91 #define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x71000000 dtb; " \
92 				"fatload mmc 0:1 0x72000000 zImage; " \
93 				"bootz 0x72000000 - 0x71000000"
94 #endif
95 
96 /*
97  * Size of malloc() pool
98  */
99 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
100 
101 /* Defines for SPL */
102 #define CONFIG_SPL_TEXT_BASE		0x300000
103 #define CONFIG_SPL_MAX_SIZE		0x010000
104 #define CONFIG_SPL_STACK		0x310000
105 
106 #define CONFIG_SYS_MONITOR_LEN		0x80000
107 
108 #ifdef CONFIG_SD_BOOT
109 
110 #define CONFIG_SPL_BSS_START_ADDR	0x70000000
111 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
112 #define CONFIG_SYS_SPL_MALLOC_START	0x70080000
113 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
114 
115 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
116 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
117 
118 #elif CONFIG_NAND_BOOT
119 #define CONFIG_SPL_NAND_DRIVERS
120 #define CONFIG_SPL_NAND_BASE
121 #define CONFIG_SPL_NAND_ECC
122 #define CONFIG_SPL_NAND_SOFTECC
123 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
124 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
125 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
126 
127 #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
128 #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
129 #define CONFIG_SYS_NAND_PAGE_COUNT	64
130 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
131 #define CONFIG_SYS_NAND_ECCSIZE		256
132 #define CONFIG_SYS_NAND_ECCBYTES	3
133 #define CONFIG_SYS_NAND_OOBSIZE		64
134 #define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
135 					  48, 49, 50, 51, 52, 53, 54, 55, \
136 					  56, 57, 58, 59, 60, 61, 62, 63, }
137 #endif
138 
139 #define CONFIG_SPL_ATMEL_SIZE
140 #define CONFIG_SYS_MASTER_CLOCK		132096000
141 #define CONFIG_SYS_AT91_PLLA		0x20c73f03
142 #define CONFIG_SYS_MCKR			0x1301
143 #define CONFIG_SYS_MCKR_CSS		0x1302
144 
145 #endif
146