1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 #define CONFIG_BOARD_EARLY_INIT_F 45 46 #define CONFIG_DISPLAY_CPUINFO 47 48 #define CONFIG_CMD_BOOTZ 49 #define CONFIG_OF_LIBFDT 50 51 #define CONFIG_SYS_GENERIC_BOARD 52 53 /* 54 * Hardware drivers 55 */ 56 #define CONFIG_ATMEL_LEGACY 57 #define CONFIG_AT91_GPIO 1 58 #define CONFIG_AT91_GPIO_PULLUP 1 59 60 /* serial console */ 61 #define CONFIG_ATMEL_USART 62 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 63 #define CONFIG_USART_ID ATMEL_ID_SYS 64 #define CONFIG_BAUDRATE 115200 65 66 /* LCD */ 67 #define CONFIG_LCD 1 68 #define LCD_BPP LCD_COLOR8 69 #define CONFIG_LCD_LOGO 1 70 #undef LCD_TEST_PATTERN 71 #define CONFIG_LCD_INFO 1 72 #define CONFIG_LCD_INFO_BELOW_LOGO 1 73 #define CONFIG_SYS_WHITE_ON_BLACK 1 74 #define CONFIG_ATMEL_LCD 1 75 #define CONFIG_ATMEL_LCD_BGR555 1 76 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 77 78 /* LED */ 79 #define CONFIG_AT91_LED 80 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 81 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 82 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 83 84 #define CONFIG_BOOTDELAY 3 85 86 /* 87 * BOOTP options 88 */ 89 #define CONFIG_BOOTP_BOOTFILESIZE 1 90 #define CONFIG_BOOTP_BOOTPATH 1 91 #define CONFIG_BOOTP_GATEWAY 1 92 #define CONFIG_BOOTP_HOSTNAME 1 93 94 /* 95 * Command line configuration. 96 */ 97 #include <config_cmd_default.h> 98 #undef CONFIG_CMD_BDI 99 #undef CONFIG_CMD_FPGA 100 #undef CONFIG_CMD_IMI 101 #undef CONFIG_CMD_IMLS 102 #undef CONFIG_CMD_LOADS 103 #undef CONFIG_CMD_SOURCE 104 105 #define CONFIG_CMD_PING 1 106 #define CONFIG_CMD_DHCP 1 107 #define CONFIG_CMD_NAND 1 108 #define CONFIG_CMD_MMC 109 #define CONFIG_CMD_USB 1 110 111 /* SDRAM */ 112 #define CONFIG_NR_DRAM_BANKS 1 113 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 114 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 115 116 #define CONFIG_SYS_INIT_SP_ADDR \ 117 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 118 119 /* DataFlash */ 120 #define CONFIG_ATMEL_DATAFLASH_SPI 121 #define CONFIG_HAS_DATAFLASH 1 122 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 123 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 124 #define AT91_SPI_CLK 15000000 125 #define DATAFLASH_TCSS (0x1a << 16) 126 #define DATAFLASH_TCHS (0x1 << 24) 127 128 /* MMC */ 129 #ifdef CONFIG_CMD_MMC 130 #define CONFIG_MMC 131 #define CONFIG_GENERIC_MMC 132 #define CONFIG_GENERIC_ATMEL_MCI 133 #endif 134 135 /* FAT */ 136 #ifdef CONFIG_CMD_FAT 137 #define CONFIG_DOS_PARTITION 138 #endif 139 140 /* NOR flash, if populated */ 141 #ifdef CONFIG_SYS_USE_NORFLASH 142 #define CONFIG_SYS_FLASH_CFI 1 143 #define CONFIG_FLASH_CFI_DRIVER 1 144 #define PHYS_FLASH_1 0x10000000 145 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 146 #define CONFIG_SYS_MAX_FLASH_SECT 256 147 #define CONFIG_SYS_MAX_FLASH_BANKS 1 148 149 #define CONFIG_SYS_MONITOR_SEC 1:0-3 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 151 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 152 #define CONFIG_ENV_IS_IN_FLASH 1 153 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 154 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 155 156 /* Address and size of Primary Environment Sector */ 157 #define CONFIG_ENV_SIZE 0x10000 158 159 #define CONFIG_EXTRA_ENV_SETTINGS \ 160 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 161 "update=" \ 162 "protect off ${monitor_base} +${filesize};" \ 163 "erase ${monitor_base} +${filesize};" \ 164 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 165 "protect on ${monitor_base} +${filesize}\0" 166 167 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 168 #define MASTER_PLL_MUL 171 169 #define MASTER_PLL_DIV 14 170 #define MASTER_PLL_OUT 3 171 172 /* clocks */ 173 #define CONFIG_SYS_MOR_VAL \ 174 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 175 #define CONFIG_SYS_PLLAR_VAL \ 176 (AT91_PMC_PLLAR_29 | \ 177 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 178 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 179 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 180 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 181 182 /* PCK/2 = MCK Master Clock from PLLA */ 183 #define CONFIG_SYS_MCKR1_VAL \ 184 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 185 AT91_PMC_MCKR_MDIV_2) 186 187 /* PCK/2 = MCK Master Clock from PLLA */ 188 #define CONFIG_SYS_MCKR2_VAL \ 189 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 190 AT91_PMC_MCKR_MDIV_2) 191 192 /* define PDC[31:16] as DATA[31:16] */ 193 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 194 /* no pull-up for D[31:16] */ 195 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 196 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 197 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 198 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 199 AT91_MATRIX_CSA_EBI_CS1A) 200 201 /* SDRAM */ 202 /* SDRAMC_MR Mode register */ 203 #define CONFIG_SYS_SDRC_MR_VAL1 0 204 /* SDRAMC_TR - Refresh Timer register */ 205 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 206 /* SDRAMC_CR - Configuration register*/ 207 #define CONFIG_SYS_SDRC_CR_VAL \ 208 (AT91_SDRAMC_NC_9 | \ 209 AT91_SDRAMC_NR_13 | \ 210 AT91_SDRAMC_NB_4 | \ 211 AT91_SDRAMC_CAS_3 | \ 212 AT91_SDRAMC_DBW_32 | \ 213 (1 << 8) | /* Write Recovery Delay */ \ 214 (7 << 12) | /* Row Cycle Delay */ \ 215 (2 << 16) | /* Row Precharge Delay */ \ 216 (2 << 20) | /* Row to Column Delay */ \ 217 (5 << 24) | /* Active to Precharge Delay */ \ 218 (1 << 28)) /* Exit Self Refresh to Active Delay */ 219 220 /* Memory Device Register -> SDRAM */ 221 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 222 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 223 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 224 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 225 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 226 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 227 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 228 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 229 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 230 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 231 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 232 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 233 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 234 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 235 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 236 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 237 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 238 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 239 240 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 241 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 242 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 243 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 244 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 245 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 246 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 247 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 248 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 249 #define CONFIG_SYS_SMC0_MODE0_VAL \ 250 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 251 AT91_SMC_MODE_DBW_16 | \ 252 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 253 254 /* user reset enable */ 255 #define CONFIG_SYS_RSTC_RMR_VAL \ 256 (AT91_RSTC_KEY | \ 257 AT91_RSTC_MR_URSTEN | \ 258 AT91_RSTC_MR_ERSTL(15)) 259 260 /* Disable Watchdog */ 261 #define CONFIG_SYS_WDTC_WDMR_VAL \ 262 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 263 AT91_WDT_MR_WDV(0xfff) | \ 264 AT91_WDT_MR_WDDIS | \ 265 AT91_WDT_MR_WDD(0xfff)) 266 267 #endif 268 269 #else 270 #define CONFIG_SYS_NO_FLASH 1 271 #endif 272 273 /* NAND flash */ 274 #ifdef CONFIG_CMD_NAND 275 #define CONFIG_NAND_ATMEL 276 #define CONFIG_SYS_MAX_NAND_DEVICE 1 277 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 278 #define CONFIG_SYS_NAND_DBW_8 1 279 /* our ALE is AD21 */ 280 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 281 /* our CLE is AD22 */ 282 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 283 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 284 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 285 #endif 286 287 /* Ethernet */ 288 #define CONFIG_MACB 1 289 #define CONFIG_RMII 1 290 #define CONFIG_NET_RETRY_COUNT 20 291 #define CONFIG_RESET_PHY_R 1 292 #define CONFIG_AT91_WANTS_COMMON_PHY 293 294 /* USB */ 295 #define CONFIG_USB_ATMEL 296 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 297 #define CONFIG_USB_OHCI_NEW 1 298 #define CONFIG_DOS_PARTITION 1 299 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 300 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 301 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 302 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 303 #define CONFIG_USB_STORAGE 1 304 #define CONFIG_CMD_FAT 1 305 306 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 307 308 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 309 #define CONFIG_SYS_MEMTEST_END 0x23e00000 310 311 #ifdef CONFIG_SYS_USE_DATAFLASH 312 313 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 314 #define CONFIG_ENV_IS_IN_DATAFLASH 1 315 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 316 #define CONFIG_ENV_OFFSET 0x4200 317 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 318 #define CONFIG_ENV_SIZE 0x4200 319 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 320 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 321 "root=/dev/mtdblock0 " \ 322 "mtdparts=atmel_nand:-(root) "\ 323 "rw rootfstype=jffs2" 324 325 #elif CONFIG_SYS_USE_NANDFLASH 326 327 /* bootstrap + u-boot + env + linux in nandflash */ 328 #define CONFIG_ENV_IS_IN_NAND 1 329 #define CONFIG_ENV_OFFSET 0xc0000 330 #define CONFIG_ENV_OFFSET_REDUND 0x100000 331 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 332 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 333 #define CONFIG_BOOTARGS \ 334 "console=ttyS0,115200 earlyprintk " \ 335 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 336 "256k(env),256k(env_redundant),256k(spare)," \ 337 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 338 "root=/dev/mtdblock7 rw rootfstype=jffs2" 339 #endif 340 341 #define CONFIG_SYS_PROMPT "U-Boot> " 342 #define CONFIG_SYS_CBSIZE 256 343 #define CONFIG_SYS_MAXARGS 16 344 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 345 #define CONFIG_SYS_LONGHELP 1 346 #define CONFIG_CMDLINE_EDITING 1 347 #define CONFIG_AUTO_COMPLETE 348 #define CONFIG_SYS_HUSH_PARSER 349 350 /* 351 * Size of malloc() pool 352 */ 353 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 354 355 #endif 356