1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 /* 45 * Hardware drivers 46 */ 47 #define CONFIG_ATMEL_LEGACY 48 #define CONFIG_AT91_GPIO 1 49 #define CONFIG_AT91_GPIO_PULLUP 1 50 51 /* serial console */ 52 #define CONFIG_ATMEL_USART 53 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 54 #define CONFIG_USART_ID ATMEL_ID_SYS 55 56 /* LCD */ 57 #define LCD_BPP LCD_COLOR8 58 #define CONFIG_LCD_LOGO 1 59 #undef LCD_TEST_PATTERN 60 #define CONFIG_LCD_INFO 1 61 #define CONFIG_LCD_INFO_BELOW_LOGO 1 62 #define CONFIG_SYS_WHITE_ON_BLACK 1 63 #define CONFIG_ATMEL_LCD 1 64 #define CONFIG_ATMEL_LCD_BGR555 1 65 66 /* LED */ 67 #define CONFIG_AT91_LED 68 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 69 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 70 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 71 72 73 /* 74 * BOOTP options 75 */ 76 #define CONFIG_BOOTP_BOOTFILESIZE 1 77 #define CONFIG_BOOTP_BOOTPATH 1 78 #define CONFIG_BOOTP_GATEWAY 1 79 #define CONFIG_BOOTP_HOSTNAME 1 80 81 /* 82 * Command line configuration. 83 */ 84 #define CONFIG_CMD_NAND 1 85 86 /* SDRAM */ 87 #define CONFIG_NR_DRAM_BANKS 1 88 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 89 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 90 91 #define CONFIG_SYS_INIT_SP_ADDR \ 92 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 93 94 /* DataFlash */ 95 #define CONFIG_ATMEL_DATAFLASH_SPI 96 #define CONFIG_HAS_DATAFLASH 1 97 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 98 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 99 #define AT91_SPI_CLK 15000000 100 #define DATAFLASH_TCSS (0x1a << 16) 101 #define DATAFLASH_TCHS (0x1 << 24) 102 103 /* MMC */ 104 #ifdef CONFIG_CMD_MMC 105 #define CONFIG_GENERIC_ATMEL_MCI 106 #endif 107 108 /* NOR flash, if populated */ 109 #ifdef CONFIG_SYS_USE_NORFLASH 110 #define CONFIG_SYS_FLASH_CFI 1 111 #define CONFIG_FLASH_CFI_DRIVER 1 112 #define PHYS_FLASH_1 0x10000000 113 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 114 #define CONFIG_SYS_MAX_FLASH_SECT 256 115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 116 117 #define CONFIG_SYS_MONITOR_SEC 1:0-3 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 119 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 120 #define CONFIG_ENV_IS_IN_FLASH 1 121 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 122 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 123 124 /* Address and size of Primary Environment Sector */ 125 #define CONFIG_ENV_SIZE 0x10000 126 127 #define CONFIG_EXTRA_ENV_SETTINGS \ 128 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 129 "update=" \ 130 "protect off ${monitor_base} +${filesize};" \ 131 "erase ${monitor_base} +${filesize};" \ 132 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 133 "protect on ${monitor_base} +${filesize}\0" 134 135 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 136 #define MASTER_PLL_MUL 171 137 #define MASTER_PLL_DIV 14 138 #define MASTER_PLL_OUT 3 139 140 /* clocks */ 141 #define CONFIG_SYS_MOR_VAL \ 142 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 143 #define CONFIG_SYS_PLLAR_VAL \ 144 (AT91_PMC_PLLAR_29 | \ 145 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 146 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 147 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 148 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 149 150 /* PCK/2 = MCK Master Clock from PLLA */ 151 #define CONFIG_SYS_MCKR1_VAL \ 152 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 153 AT91_PMC_MCKR_MDIV_2) 154 155 /* PCK/2 = MCK Master Clock from PLLA */ 156 #define CONFIG_SYS_MCKR2_VAL \ 157 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 158 AT91_PMC_MCKR_MDIV_2) 159 160 /* define PDC[31:16] as DATA[31:16] */ 161 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 162 /* no pull-up for D[31:16] */ 163 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 164 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 165 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 166 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 167 AT91_MATRIX_CSA_EBI_CS1A) 168 169 /* SDRAM */ 170 /* SDRAMC_MR Mode register */ 171 #define CONFIG_SYS_SDRC_MR_VAL1 0 172 /* SDRAMC_TR - Refresh Timer register */ 173 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 174 /* SDRAMC_CR - Configuration register*/ 175 #define CONFIG_SYS_SDRC_CR_VAL \ 176 (AT91_SDRAMC_NC_9 | \ 177 AT91_SDRAMC_NR_13 | \ 178 AT91_SDRAMC_NB_4 | \ 179 AT91_SDRAMC_CAS_3 | \ 180 AT91_SDRAMC_DBW_32 | \ 181 (1 << 8) | /* Write Recovery Delay */ \ 182 (7 << 12) | /* Row Cycle Delay */ \ 183 (2 << 16) | /* Row Precharge Delay */ \ 184 (2 << 20) | /* Row to Column Delay */ \ 185 (5 << 24) | /* Active to Precharge Delay */ \ 186 (1 << 28)) /* Exit Self Refresh to Active Delay */ 187 188 /* Memory Device Register -> SDRAM */ 189 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 190 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 191 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 192 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 193 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 194 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 195 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 196 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 197 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 198 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 199 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 200 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 201 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 202 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 203 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 204 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 205 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 206 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 207 208 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 209 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 210 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 211 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 212 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 213 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 214 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 215 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 216 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 217 #define CONFIG_SYS_SMC0_MODE0_VAL \ 218 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 219 AT91_SMC_MODE_DBW_16 | \ 220 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 221 222 /* user reset enable */ 223 #define CONFIG_SYS_RSTC_RMR_VAL \ 224 (AT91_RSTC_KEY | \ 225 AT91_RSTC_MR_URSTEN | \ 226 AT91_RSTC_MR_ERSTL(15)) 227 228 /* Disable Watchdog */ 229 #define CONFIG_SYS_WDTC_WDMR_VAL \ 230 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 231 AT91_WDT_MR_WDV(0xfff) | \ 232 AT91_WDT_MR_WDDIS | \ 233 AT91_WDT_MR_WDD(0xfff)) 234 235 #endif 236 #endif 237 238 /* NAND flash */ 239 #ifdef CONFIG_CMD_NAND 240 #define CONFIG_NAND_ATMEL 241 #define CONFIG_SYS_MAX_NAND_DEVICE 1 242 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 243 #define CONFIG_SYS_NAND_DBW_8 1 244 /* our ALE is AD21 */ 245 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 246 /* our CLE is AD22 */ 247 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 248 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 249 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 250 #endif 251 252 /* Ethernet */ 253 #define CONFIG_MACB 1 254 #define CONFIG_RMII 1 255 #define CONFIG_NET_RETRY_COUNT 20 256 #define CONFIG_RESET_PHY_R 1 257 #define CONFIG_AT91_WANTS_COMMON_PHY 258 259 /* USB */ 260 #define CONFIG_USB_ATMEL 261 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 262 #define CONFIG_USB_OHCI_NEW 1 263 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 264 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 265 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 266 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 267 268 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 269 270 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 271 #define CONFIG_SYS_MEMTEST_END 0x23e00000 272 273 #ifdef CONFIG_SYS_USE_DATAFLASH 274 275 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 276 #define CONFIG_ENV_IS_IN_DATAFLASH 1 277 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 278 #define CONFIG_ENV_OFFSET 0x4200 279 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 280 #define CONFIG_ENV_SIZE 0x4200 281 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 282 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 283 "root=/dev/mtdblock0 " \ 284 "mtdparts=atmel_nand:-(root) "\ 285 "rw rootfstype=jffs2" 286 287 #elif CONFIG_SYS_USE_NANDFLASH 288 289 /* bootstrap + u-boot + env + linux in nandflash */ 290 #define CONFIG_ENV_IS_IN_NAND 1 291 #define CONFIG_ENV_OFFSET 0xc0000 292 #define CONFIG_ENV_OFFSET_REDUND 0x100000 293 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 294 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 295 #define CONFIG_BOOTARGS \ 296 "console=ttyS0,115200 earlyprintk " \ 297 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 298 "256k(env),256k(env_redundant),256k(spare)," \ 299 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 300 "root=/dev/mtdblock7 rw rootfstype=jffs2" 301 #endif 302 303 #define CONFIG_SYS_CBSIZE 256 304 #define CONFIG_SYS_MAXARGS 16 305 #define CONFIG_SYS_LONGHELP 1 306 #define CONFIG_CMDLINE_EDITING 1 307 #define CONFIG_AUTO_COMPLETE 308 309 /* 310 * Size of malloc() pool 311 */ 312 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 313 314 #endif 315