1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9263EK board.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * SoC must be defined first, before hardware.h is included.
16  * In this case SoC is defined in boards.cfg.
17  */
18 #include <asm/hardware.h>
19 
20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
21 #define CONFIG_SYS_TEXT_BASE		0x21F00000
22 #else
23 #define CONFIG_SYS_TEXT_BASE		0x0000000
24 #endif
25 
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
29 
30 #define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
31 
32 #define CONFIG_ARCH_CPU_INIT
33 
34 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36 #define CONFIG_INITRD_TAG	1
37 
38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
39 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #else
41 #define CONFIG_SYS_USE_NORFLASH
42 #endif
43 
44 #define CONFIG_BOARD_EARLY_INIT_F
45 
46 #define CONFIG_DISPLAY_CPUINFO
47 
48 /*
49  * Hardware drivers
50  */
51 #define CONFIG_ATMEL_LEGACY
52 #define CONFIG_AT91_GPIO		1
53 #define CONFIG_AT91_GPIO_PULLUP		1
54 
55 /* serial console */
56 #define CONFIG_ATMEL_USART
57 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
58 #define CONFIG_USART_ID			ATMEL_ID_SYS
59 #define CONFIG_BAUDRATE			115200
60 
61 /* LCD */
62 #define CONFIG_LCD			1
63 #define LCD_BPP				LCD_COLOR8
64 #define CONFIG_LCD_LOGO			1
65 #undef LCD_TEST_PATTERN
66 #define CONFIG_LCD_INFO			1
67 #define CONFIG_LCD_INFO_BELOW_LOGO	1
68 #define CONFIG_SYS_WHITE_ON_BLACK	1
69 #define CONFIG_ATMEL_LCD		1
70 #define CONFIG_ATMEL_LCD_BGR555		1
71 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
72 
73 /* LED */
74 #define CONFIG_AT91_LED
75 #define	CONFIG_RED_LED		AT91_PIN_PB7	/* the power led */
76 #define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
77 #define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
78 
79 
80 /*
81  * BOOTP options
82  */
83 #define CONFIG_BOOTP_BOOTFILESIZE	1
84 #define CONFIG_BOOTP_BOOTPATH		1
85 #define CONFIG_BOOTP_GATEWAY		1
86 #define CONFIG_BOOTP_HOSTNAME		1
87 
88 /*
89  * Command line configuration.
90  */
91 #define CONFIG_CMD_NAND		1
92 
93 /* SDRAM */
94 #define CONFIG_NR_DRAM_BANKS		1
95 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
96 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
97 
98 #define CONFIG_SYS_INIT_SP_ADDR \
99 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
100 
101 /* DataFlash */
102 #define CONFIG_ATMEL_DATAFLASH_SPI
103 #define CONFIG_HAS_DATAFLASH		1
104 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
105 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
106 #define AT91_SPI_CLK			15000000
107 #define DATAFLASH_TCSS			(0x1a << 16)
108 #define DATAFLASH_TCHS			(0x1 << 24)
109 
110 /* MMC */
111 #ifdef CONFIG_CMD_MMC
112 #define CONFIG_MMC
113 #define CONFIG_GENERIC_MMC
114 #define CONFIG_GENERIC_ATMEL_MCI
115 #endif
116 
117 /* NOR flash, if populated */
118 #ifdef CONFIG_SYS_USE_NORFLASH
119 #define CONFIG_SYS_FLASH_CFI			1
120 #define CONFIG_FLASH_CFI_DRIVER			1
121 #define PHYS_FLASH_1				0x10000000
122 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
123 #define CONFIG_SYS_MAX_FLASH_SECT		256
124 #define CONFIG_SYS_MAX_FLASH_BANKS		1
125 
126 #define CONFIG_SYS_MONITOR_SEC	1:0-3
127 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
128 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
129 #define CONFIG_ENV_IS_IN_FLASH	1
130 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
131 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
132 
133 /* Address and size of Primary Environment Sector */
134 #define CONFIG_ENV_SIZE		0x10000
135 
136 #define CONFIG_EXTRA_ENV_SETTINGS	\
137 	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
138 	"update=" \
139 		"protect off ${monitor_base} +${filesize};" \
140 		"erase ${monitor_base} +${filesize};" \
141 		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
142 		"protect on ${monitor_base} +${filesize}\0"
143 
144 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
145 #define MASTER_PLL_MUL		171
146 #define MASTER_PLL_DIV		14
147 #define MASTER_PLL_OUT		3
148 
149 /* clocks */
150 #define CONFIG_SYS_MOR_VAL						\
151 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
152 #define CONFIG_SYS_PLLAR_VAL					\
153 	(AT91_PMC_PLLAR_29 |					\
154 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
155 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
156 	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
157 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
158 
159 /* PCK/2 = MCK Master Clock from PLLA */
160 #define	CONFIG_SYS_MCKR1_VAL		\
161 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
162 	 AT91_PMC_MCKR_MDIV_2)
163 
164 /* PCK/2 = MCK Master Clock from PLLA */
165 #define	CONFIG_SYS_MCKR2_VAL		\
166 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
167 	AT91_PMC_MCKR_MDIV_2)
168 
169 /* define PDC[31:16] as DATA[31:16] */
170 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
171 /* no pull-up for D[31:16] */
172 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
173 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
174 #define CONFIG_SYS_MATRIX_EBICSA_VAL					\
175 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
176 	 AT91_MATRIX_CSA_EBI_CS1A)
177 
178 /* SDRAM */
179 /* SDRAMC_MR Mode register */
180 #define CONFIG_SYS_SDRC_MR_VAL1		0
181 /* SDRAMC_TR - Refresh Timer register */
182 #define CONFIG_SYS_SDRC_TR_VAL1		0x13C
183 /* SDRAMC_CR - Configuration register*/
184 #define CONFIG_SYS_SDRC_CR_VAL							\
185 		(AT91_SDRAMC_NC_9 |						\
186 		 AT91_SDRAMC_NR_13 |						\
187 		 AT91_SDRAMC_NB_4 |						\
188 		 AT91_SDRAMC_CAS_3 |						\
189 		 AT91_SDRAMC_DBW_32 |						\
190 		 (1 <<  8) |		/* Write Recovery Delay */		\
191 		 (7 << 12) |		/* Row Cycle Delay */			\
192 		 (2 << 16) |		/* Row Precharge Delay */		\
193 		 (2 << 20) |		/* Row to Column Delay */		\
194 		 (5 << 24) |		/* Active to Precharge Delay */		\
195 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
196 
197 /* Memory Device Register -> SDRAM */
198 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
199 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
200 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
201 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
202 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
203 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
204 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
205 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
206 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
207 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
208 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
209 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
210 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
211 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
212 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
213 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
214 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
215 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
216 
217 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
218 #define CONFIG_SYS_SMC0_SETUP0_VAL				\
219 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
220 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
221 #define CONFIG_SYS_SMC0_PULSE0_VAL				\
222 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
223 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
224 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
225 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
226 #define CONFIG_SYS_SMC0_MODE0_VAL				\
227 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
228 	 AT91_SMC_MODE_DBW_16 |					\
229 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
230 
231 /* user reset enable */
232 #define CONFIG_SYS_RSTC_RMR_VAL			\
233 		(AT91_RSTC_KEY |		\
234 		AT91_RSTC_MR_URSTEN |		\
235 		AT91_RSTC_MR_ERSTL(15))
236 
237 /* Disable Watchdog */
238 #define CONFIG_SYS_WDTC_WDMR_VAL				\
239 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
240 		 AT91_WDT_MR_WDV(0xfff) |			\
241 		 AT91_WDT_MR_WDDIS |				\
242 		 AT91_WDT_MR_WDD(0xfff))
243 
244 #endif
245 
246 #else
247 #define CONFIG_SYS_NO_FLASH			1
248 #endif
249 
250 /* NAND flash */
251 #ifdef CONFIG_CMD_NAND
252 #define CONFIG_NAND_ATMEL
253 #define CONFIG_SYS_MAX_NAND_DEVICE		1
254 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
255 #define CONFIG_SYS_NAND_DBW_8			1
256 /* our ALE is AD21 */
257 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
258 /* our CLE is AD22 */
259 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
260 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
261 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
262 #endif
263 
264 /* Ethernet */
265 #define CONFIG_MACB			1
266 #define CONFIG_RMII			1
267 #define CONFIG_NET_RETRY_COUNT		20
268 #define CONFIG_RESET_PHY_R		1
269 #define CONFIG_AT91_WANTS_COMMON_PHY
270 
271 /* USB */
272 #define CONFIG_USB_ATMEL
273 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
274 #define CONFIG_USB_OHCI_NEW		1
275 #define CONFIG_DOS_PARTITION		1
276 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
277 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
278 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
279 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
280 #define CONFIG_USB_STORAGE		1
281 
282 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
283 
284 #define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
285 #define CONFIG_SYS_MEMTEST_END			0x23e00000
286 
287 #ifdef CONFIG_SYS_USE_DATAFLASH
288 
289 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
290 #define CONFIG_ENV_IS_IN_DATAFLASH	1
291 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
292 #define CONFIG_ENV_OFFSET		0x4200
293 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
294 #define CONFIG_ENV_SIZE		0x4200
295 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
296 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
297 				"root=/dev/mtdblock0 " \
298 				"mtdparts=atmel_nand:-(root) "\
299 				"rw rootfstype=jffs2"
300 
301 #elif CONFIG_SYS_USE_NANDFLASH
302 
303 /* bootstrap + u-boot + env + linux in nandflash */
304 #define CONFIG_ENV_IS_IN_NAND		1
305 #define CONFIG_ENV_OFFSET		0xc0000
306 #define CONFIG_ENV_OFFSET_REDUND	0x100000
307 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
308 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
309 #define CONFIG_BOOTARGS							\
310 	"console=ttyS0,115200 earlyprintk "				\
311 	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
312 	"256k(env),256k(env_redundant),256k(spare),"			\
313 	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
314 	"root=/dev/mtdblock7 rw rootfstype=jffs2"
315 #endif
316 
317 #define CONFIG_SYS_CBSIZE		256
318 #define CONFIG_SYS_MAXARGS		16
319 #define CONFIG_SYS_LONGHELP		1
320 #define CONFIG_CMDLINE_EDITING		1
321 #define CONFIG_AUTO_COMPLETE
322 
323 /*
324  * Size of malloc() pool
325  */
326 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
327 
328 #endif
329