1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2007-2008
4  * Stelian Pop <stelian@popies.net>
5  * Lead Tech Design <www.leadtechdesign.com>
6  *
7  * Configuation settings for the AT91SAM9263EK board.
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /*
14  * SoC must be defined first, before hardware.h is included.
15  * In this case SoC is defined in boards.cfg.
16  */
17 #include <asm/hardware.h>
18 
19 /* ARM asynchronous clock */
20 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
21 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
22 
23 #define CONFIG_ARCH_CPU_INIT
24 
25 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
26 #define CONFIG_SETUP_MEMORY_TAGS 1
27 #define CONFIG_INITRD_TAG	1
28 
29 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
30 #define CONFIG_SKIP_LOWLEVEL_INIT
31 #else
32 #define CONFIG_SYS_USE_NORFLASH
33 #endif
34 
35 /*
36  * Hardware drivers
37  */
38 #define CONFIG_ATMEL_LEGACY
39 
40 /* LCD */
41 #define LCD_BPP				LCD_COLOR8
42 #define CONFIG_LCD_LOGO			1
43 #undef LCD_TEST_PATTERN
44 #define CONFIG_LCD_INFO			1
45 #define CONFIG_LCD_INFO_BELOW_LOGO	1
46 #define CONFIG_ATMEL_LCD		1
47 #define CONFIG_ATMEL_LCD_BGR555		1
48 
49 /*
50  * BOOTP options
51  */
52 #define CONFIG_BOOTP_BOOTFILESIZE	1
53 
54 /* SDRAM */
55 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
56 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
57 
58 #define CONFIG_SYS_INIT_SP_ADDR \
59 	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
60 
61 /* NOR flash, if populated */
62 #ifdef CONFIG_SYS_USE_NORFLASH
63 #define PHYS_FLASH_1				0x10000000
64 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
65 #define CONFIG_SYS_MAX_FLASH_SECT		256
66 #define CONFIG_SYS_MAX_FLASH_BANKS		1
67 
68 #define CONFIG_SYS_MONITOR_SEC	1:0-3
69 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
70 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
71 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
72 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
73 
74 /* Address and size of Primary Environment Sector */
75 #define CONFIG_ENV_SIZE		0x10000
76 
77 #define CONFIG_EXTRA_ENV_SETTINGS	\
78 	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
79 	"update=" \
80 		"protect off ${monitor_base} +${filesize};" \
81 		"erase ${monitor_base} +${filesize};" \
82 		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
83 		"protect on ${monitor_base} +${filesize}\0"
84 
85 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
86 #define MASTER_PLL_MUL		171
87 #define MASTER_PLL_DIV		14
88 #define MASTER_PLL_OUT		3
89 
90 /* clocks */
91 #define CONFIG_SYS_MOR_VAL						\
92 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
93 #define CONFIG_SYS_PLLAR_VAL					\
94 	(AT91_PMC_PLLAR_29 |					\
95 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
96 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
97 	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
98 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
99 
100 /* PCK/2 = MCK Master Clock from PLLA */
101 #define	CONFIG_SYS_MCKR1_VAL		\
102 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
103 	 AT91_PMC_MCKR_MDIV_2)
104 
105 /* PCK/2 = MCK Master Clock from PLLA */
106 #define	CONFIG_SYS_MCKR2_VAL		\
107 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
108 	AT91_PMC_MCKR_MDIV_2)
109 
110 /* define PDC[31:16] as DATA[31:16] */
111 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
112 /* no pull-up for D[31:16] */
113 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
114 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
115 #define CONFIG_SYS_MATRIX_EBICSA_VAL					\
116 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
117 	 AT91_MATRIX_CSA_EBI_CS1A)
118 
119 /* SDRAM */
120 /* SDRAMC_MR Mode register */
121 #define CONFIG_SYS_SDRC_MR_VAL1		0
122 /* SDRAMC_TR - Refresh Timer register */
123 #define CONFIG_SYS_SDRC_TR_VAL1		0x13C
124 /* SDRAMC_CR - Configuration register*/
125 #define CONFIG_SYS_SDRC_CR_VAL							\
126 		(AT91_SDRAMC_NC_9 |						\
127 		 AT91_SDRAMC_NR_13 |						\
128 		 AT91_SDRAMC_NB_4 |						\
129 		 AT91_SDRAMC_CAS_3 |						\
130 		 AT91_SDRAMC_DBW_32 |						\
131 		 (1 <<  8) |		/* Write Recovery Delay */		\
132 		 (7 << 12) |		/* Row Cycle Delay */			\
133 		 (2 << 16) |		/* Row Precharge Delay */		\
134 		 (2 << 20) |		/* Row to Column Delay */		\
135 		 (5 << 24) |		/* Active to Precharge Delay */		\
136 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
137 
138 /* Memory Device Register -> SDRAM */
139 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
140 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
141 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
142 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
143 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
144 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
145 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
146 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
147 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
148 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
149 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
150 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
151 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
152 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
153 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
154 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
155 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
156 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
157 
158 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
159 #define CONFIG_SYS_SMC0_SETUP0_VAL				\
160 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
161 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
162 #define CONFIG_SYS_SMC0_PULSE0_VAL				\
163 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
164 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
165 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
166 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
167 #define CONFIG_SYS_SMC0_MODE0_VAL				\
168 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
169 	 AT91_SMC_MODE_DBW_16 |					\
170 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
171 
172 /* user reset enable */
173 #define CONFIG_SYS_RSTC_RMR_VAL			\
174 		(AT91_RSTC_KEY |		\
175 		AT91_RSTC_MR_URSTEN |		\
176 		AT91_RSTC_MR_ERSTL(15))
177 
178 /* Disable Watchdog */
179 #define CONFIG_SYS_WDTC_WDMR_VAL				\
180 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
181 		 AT91_WDT_MR_WDV(0xfff) |			\
182 		 AT91_WDT_MR_WDDIS |				\
183 		 AT91_WDT_MR_WDD(0xfff))
184 
185 #endif
186 #endif
187 
188 /* NAND flash */
189 #ifdef CONFIG_CMD_NAND
190 #define CONFIG_SYS_MAX_NAND_DEVICE		1
191 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
192 #define CONFIG_SYS_NAND_DBW_8			1
193 /* our ALE is AD21 */
194 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
195 /* our CLE is AD22 */
196 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
197 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
198 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
199 #endif
200 
201 /* Ethernet */
202 #define CONFIG_RESET_PHY_R		1
203 #define CONFIG_AT91_WANTS_COMMON_PHY
204 
205 /* USB */
206 #define CONFIG_USB_ATMEL
207 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
208 #define CONFIG_USB_OHCI_NEW		1
209 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
210 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
211 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
212 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
213 
214 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
215 
216 #define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
217 #define CONFIG_SYS_MEMTEST_END			0x23e00000
218 
219 #ifdef CONFIG_SYS_USE_DATAFLASH
220 
221 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
222 #define CONFIG_ENV_OFFSET	0x4200
223 #define CONFIG_ENV_SIZE		0x4200
224 #define CONFIG_ENV_SECT_SIZE	0x210
225 #define CONFIG_ENV_SPI_MAX_HZ	15000000
226 #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
227 				"sf read 0x22000000 0x84000 0x294000; " \
228 				"bootm 0x22000000"
229 
230 #elif CONFIG_SYS_USE_NANDFLASH
231 
232 /* bootstrap + u-boot + env + linux in nandflash */
233 #define CONFIG_ENV_OFFSET		0x140000
234 #define CONFIG_ENV_OFFSET_REDUND	0x100000
235 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
236 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
237 #endif
238 
239 /*
240  * Size of malloc() pool
241  */
242 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
243 
244 #endif
245