1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 /* 45 * Hardware drivers 46 */ 47 #define CONFIG_ATMEL_LEGACY 48 #define CONFIG_AT91_GPIO 1 49 #define CONFIG_AT91_GPIO_PULLUP 1 50 51 /* serial console */ 52 #define CONFIG_ATMEL_USART 53 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 54 #define CONFIG_USART_ID ATMEL_ID_SYS 55 #define CONFIG_BAUDRATE 115200 56 57 /* LCD */ 58 #define LCD_BPP LCD_COLOR8 59 #define CONFIG_LCD_LOGO 1 60 #undef LCD_TEST_PATTERN 61 #define CONFIG_LCD_INFO 1 62 #define CONFIG_LCD_INFO_BELOW_LOGO 1 63 #define CONFIG_SYS_WHITE_ON_BLACK 1 64 #define CONFIG_ATMEL_LCD 1 65 #define CONFIG_ATMEL_LCD_BGR555 1 66 67 /* LED */ 68 #define CONFIG_AT91_LED 69 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 70 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 71 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 72 73 74 /* 75 * BOOTP options 76 */ 77 #define CONFIG_BOOTP_BOOTFILESIZE 1 78 #define CONFIG_BOOTP_BOOTPATH 1 79 #define CONFIG_BOOTP_GATEWAY 1 80 #define CONFIG_BOOTP_HOSTNAME 1 81 82 /* 83 * Command line configuration. 84 */ 85 #define CONFIG_CMD_NAND 1 86 87 /* SDRAM */ 88 #define CONFIG_NR_DRAM_BANKS 1 89 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 90 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 91 92 #define CONFIG_SYS_INIT_SP_ADDR \ 93 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 94 95 /* DataFlash */ 96 #define CONFIG_ATMEL_DATAFLASH_SPI 97 #define CONFIG_HAS_DATAFLASH 1 98 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 99 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 100 #define AT91_SPI_CLK 15000000 101 #define DATAFLASH_TCSS (0x1a << 16) 102 #define DATAFLASH_TCHS (0x1 << 24) 103 104 /* MMC */ 105 #ifdef CONFIG_CMD_MMC 106 #define CONFIG_GENERIC_MMC 107 #define CONFIG_GENERIC_ATMEL_MCI 108 #endif 109 110 /* NOR flash, if populated */ 111 #ifdef CONFIG_SYS_USE_NORFLASH 112 #define CONFIG_SYS_FLASH_CFI 1 113 #define CONFIG_FLASH_CFI_DRIVER 1 114 #define PHYS_FLASH_1 0x10000000 115 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 116 #define CONFIG_SYS_MAX_FLASH_SECT 256 117 #define CONFIG_SYS_MAX_FLASH_BANKS 1 118 119 #define CONFIG_SYS_MONITOR_SEC 1:0-3 120 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 121 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 122 #define CONFIG_ENV_IS_IN_FLASH 1 123 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 124 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 125 126 /* Address and size of Primary Environment Sector */ 127 #define CONFIG_ENV_SIZE 0x10000 128 129 #define CONFIG_EXTRA_ENV_SETTINGS \ 130 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 131 "update=" \ 132 "protect off ${monitor_base} +${filesize};" \ 133 "erase ${monitor_base} +${filesize};" \ 134 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 135 "protect on ${monitor_base} +${filesize}\0" 136 137 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 138 #define MASTER_PLL_MUL 171 139 #define MASTER_PLL_DIV 14 140 #define MASTER_PLL_OUT 3 141 142 /* clocks */ 143 #define CONFIG_SYS_MOR_VAL \ 144 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 145 #define CONFIG_SYS_PLLAR_VAL \ 146 (AT91_PMC_PLLAR_29 | \ 147 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 148 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 149 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 150 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 151 152 /* PCK/2 = MCK Master Clock from PLLA */ 153 #define CONFIG_SYS_MCKR1_VAL \ 154 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 155 AT91_PMC_MCKR_MDIV_2) 156 157 /* PCK/2 = MCK Master Clock from PLLA */ 158 #define CONFIG_SYS_MCKR2_VAL \ 159 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 160 AT91_PMC_MCKR_MDIV_2) 161 162 /* define PDC[31:16] as DATA[31:16] */ 163 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 164 /* no pull-up for D[31:16] */ 165 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 166 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 167 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 168 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 169 AT91_MATRIX_CSA_EBI_CS1A) 170 171 /* SDRAM */ 172 /* SDRAMC_MR Mode register */ 173 #define CONFIG_SYS_SDRC_MR_VAL1 0 174 /* SDRAMC_TR - Refresh Timer register */ 175 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 176 /* SDRAMC_CR - Configuration register*/ 177 #define CONFIG_SYS_SDRC_CR_VAL \ 178 (AT91_SDRAMC_NC_9 | \ 179 AT91_SDRAMC_NR_13 | \ 180 AT91_SDRAMC_NB_4 | \ 181 AT91_SDRAMC_CAS_3 | \ 182 AT91_SDRAMC_DBW_32 | \ 183 (1 << 8) | /* Write Recovery Delay */ \ 184 (7 << 12) | /* Row Cycle Delay */ \ 185 (2 << 16) | /* Row Precharge Delay */ \ 186 (2 << 20) | /* Row to Column Delay */ \ 187 (5 << 24) | /* Active to Precharge Delay */ \ 188 (1 << 28)) /* Exit Self Refresh to Active Delay */ 189 190 /* Memory Device Register -> SDRAM */ 191 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 192 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 193 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 194 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 195 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 196 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 197 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 198 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 199 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 200 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 201 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 202 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 203 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 204 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 205 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 206 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 207 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 208 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 209 210 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 211 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 212 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 213 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 214 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 215 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 216 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 217 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 218 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 219 #define CONFIG_SYS_SMC0_MODE0_VAL \ 220 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 221 AT91_SMC_MODE_DBW_16 | \ 222 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 223 224 /* user reset enable */ 225 #define CONFIG_SYS_RSTC_RMR_VAL \ 226 (AT91_RSTC_KEY | \ 227 AT91_RSTC_MR_URSTEN | \ 228 AT91_RSTC_MR_ERSTL(15)) 229 230 /* Disable Watchdog */ 231 #define CONFIG_SYS_WDTC_WDMR_VAL \ 232 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 233 AT91_WDT_MR_WDV(0xfff) | \ 234 AT91_WDT_MR_WDDIS | \ 235 AT91_WDT_MR_WDD(0xfff)) 236 237 #endif 238 239 #else 240 #define CONFIG_SYS_NO_FLASH 1 241 #endif 242 243 /* NAND flash */ 244 #ifdef CONFIG_CMD_NAND 245 #define CONFIG_NAND_ATMEL 246 #define CONFIG_SYS_MAX_NAND_DEVICE 1 247 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 248 #define CONFIG_SYS_NAND_DBW_8 1 249 /* our ALE is AD21 */ 250 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 251 /* our CLE is AD22 */ 252 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 253 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 254 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 255 #endif 256 257 /* Ethernet */ 258 #define CONFIG_MACB 1 259 #define CONFIG_RMII 1 260 #define CONFIG_NET_RETRY_COUNT 20 261 #define CONFIG_RESET_PHY_R 1 262 #define CONFIG_AT91_WANTS_COMMON_PHY 263 264 /* USB */ 265 #define CONFIG_USB_ATMEL 266 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 267 #define CONFIG_USB_OHCI_NEW 1 268 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 269 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 270 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 271 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 272 273 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 274 275 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 276 #define CONFIG_SYS_MEMTEST_END 0x23e00000 277 278 #ifdef CONFIG_SYS_USE_DATAFLASH 279 280 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 281 #define CONFIG_ENV_IS_IN_DATAFLASH 1 282 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 283 #define CONFIG_ENV_OFFSET 0x4200 284 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 285 #define CONFIG_ENV_SIZE 0x4200 286 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 287 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 288 "root=/dev/mtdblock0 " \ 289 "mtdparts=atmel_nand:-(root) "\ 290 "rw rootfstype=jffs2" 291 292 #elif CONFIG_SYS_USE_NANDFLASH 293 294 /* bootstrap + u-boot + env + linux in nandflash */ 295 #define CONFIG_ENV_IS_IN_NAND 1 296 #define CONFIG_ENV_OFFSET 0xc0000 297 #define CONFIG_ENV_OFFSET_REDUND 0x100000 298 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 299 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 300 #define CONFIG_BOOTARGS \ 301 "console=ttyS0,115200 earlyprintk " \ 302 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 303 "256k(env),256k(env_redundant),256k(spare)," \ 304 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 305 "root=/dev/mtdblock7 rw rootfstype=jffs2" 306 #endif 307 308 #define CONFIG_SYS_CBSIZE 256 309 #define CONFIG_SYS_MAXARGS 16 310 #define CONFIG_SYS_LONGHELP 1 311 #define CONFIG_CMDLINE_EDITING 1 312 #define CONFIG_AUTO_COMPLETE 313 314 /* 315 * Size of malloc() pool 316 */ 317 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 318 319 #endif 320