1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 /* 45 * Hardware drivers 46 */ 47 #define CONFIG_ATMEL_LEGACY 48 49 /* LCD */ 50 #define LCD_BPP LCD_COLOR8 51 #define CONFIG_LCD_LOGO 1 52 #undef LCD_TEST_PATTERN 53 #define CONFIG_LCD_INFO 1 54 #define CONFIG_LCD_INFO_BELOW_LOGO 1 55 #define CONFIG_ATMEL_LCD 1 56 #define CONFIG_ATMEL_LCD_BGR555 1 57 58 /* 59 * BOOTP options 60 */ 61 #define CONFIG_BOOTP_BOOTFILESIZE 1 62 #define CONFIG_BOOTP_BOOTPATH 1 63 #define CONFIG_BOOTP_GATEWAY 1 64 #define CONFIG_BOOTP_HOSTNAME 1 65 66 /* SDRAM */ 67 #define CONFIG_NR_DRAM_BANKS 1 68 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 69 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 70 71 #define CONFIG_SYS_INIT_SP_ADDR \ 72 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 73 74 /* NOR flash, if populated */ 75 #ifdef CONFIG_SYS_USE_NORFLASH 76 #define CONFIG_SYS_FLASH_CFI 1 77 #define CONFIG_FLASH_CFI_DRIVER 1 78 #define PHYS_FLASH_1 0x10000000 79 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 80 #define CONFIG_SYS_MAX_FLASH_SECT 256 81 #define CONFIG_SYS_MAX_FLASH_BANKS 1 82 83 #define CONFIG_SYS_MONITOR_SEC 1:0-3 84 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 85 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 86 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 87 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 88 89 /* Address and size of Primary Environment Sector */ 90 #define CONFIG_ENV_SIZE 0x10000 91 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 94 "update=" \ 95 "protect off ${monitor_base} +${filesize};" \ 96 "erase ${monitor_base} +${filesize};" \ 97 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 98 "protect on ${monitor_base} +${filesize}\0" 99 100 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 101 #define MASTER_PLL_MUL 171 102 #define MASTER_PLL_DIV 14 103 #define MASTER_PLL_OUT 3 104 105 /* clocks */ 106 #define CONFIG_SYS_MOR_VAL \ 107 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 108 #define CONFIG_SYS_PLLAR_VAL \ 109 (AT91_PMC_PLLAR_29 | \ 110 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 111 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 112 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 113 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 114 115 /* PCK/2 = MCK Master Clock from PLLA */ 116 #define CONFIG_SYS_MCKR1_VAL \ 117 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 118 AT91_PMC_MCKR_MDIV_2) 119 120 /* PCK/2 = MCK Master Clock from PLLA */ 121 #define CONFIG_SYS_MCKR2_VAL \ 122 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 123 AT91_PMC_MCKR_MDIV_2) 124 125 /* define PDC[31:16] as DATA[31:16] */ 126 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 127 /* no pull-up for D[31:16] */ 128 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 129 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 130 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 131 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 132 AT91_MATRIX_CSA_EBI_CS1A) 133 134 /* SDRAM */ 135 /* SDRAMC_MR Mode register */ 136 #define CONFIG_SYS_SDRC_MR_VAL1 0 137 /* SDRAMC_TR - Refresh Timer register */ 138 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 139 /* SDRAMC_CR - Configuration register*/ 140 #define CONFIG_SYS_SDRC_CR_VAL \ 141 (AT91_SDRAMC_NC_9 | \ 142 AT91_SDRAMC_NR_13 | \ 143 AT91_SDRAMC_NB_4 | \ 144 AT91_SDRAMC_CAS_3 | \ 145 AT91_SDRAMC_DBW_32 | \ 146 (1 << 8) | /* Write Recovery Delay */ \ 147 (7 << 12) | /* Row Cycle Delay */ \ 148 (2 << 16) | /* Row Precharge Delay */ \ 149 (2 << 20) | /* Row to Column Delay */ \ 150 (5 << 24) | /* Active to Precharge Delay */ \ 151 (1 << 28)) /* Exit Self Refresh to Active Delay */ 152 153 /* Memory Device Register -> SDRAM */ 154 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 155 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 156 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 157 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 158 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 159 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 160 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 161 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 162 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 163 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 164 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 165 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 166 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 167 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 168 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 169 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 170 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 171 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 172 173 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 174 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 175 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 176 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 177 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 178 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 179 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 180 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 181 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 182 #define CONFIG_SYS_SMC0_MODE0_VAL \ 183 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 184 AT91_SMC_MODE_DBW_16 | \ 185 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 186 187 /* user reset enable */ 188 #define CONFIG_SYS_RSTC_RMR_VAL \ 189 (AT91_RSTC_KEY | \ 190 AT91_RSTC_MR_URSTEN | \ 191 AT91_RSTC_MR_ERSTL(15)) 192 193 /* Disable Watchdog */ 194 #define CONFIG_SYS_WDTC_WDMR_VAL \ 195 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 196 AT91_WDT_MR_WDV(0xfff) | \ 197 AT91_WDT_MR_WDDIS | \ 198 AT91_WDT_MR_WDD(0xfff)) 199 200 #endif 201 #endif 202 203 /* NAND flash */ 204 #ifdef CONFIG_CMD_NAND 205 #define CONFIG_NAND_ATMEL 206 #define CONFIG_SYS_MAX_NAND_DEVICE 1 207 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 208 #define CONFIG_SYS_NAND_DBW_8 1 209 /* our ALE is AD21 */ 210 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 211 /* our CLE is AD22 */ 212 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 213 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 214 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 215 #endif 216 217 /* Ethernet */ 218 #define CONFIG_RESET_PHY_R 1 219 #define CONFIG_AT91_WANTS_COMMON_PHY 220 221 /* USB */ 222 #define CONFIG_USB_ATMEL 223 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 224 #define CONFIG_USB_OHCI_NEW 1 225 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 226 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 227 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 228 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 229 230 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 231 232 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 233 #define CONFIG_SYS_MEMTEST_END 0x23e00000 234 235 #ifdef CONFIG_SYS_USE_DATAFLASH 236 237 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 238 #define CONFIG_ENV_OFFSET 0x4200 239 #define CONFIG_ENV_SIZE 0x4200 240 #define CONFIG_ENV_SECT_SIZE 0x210 241 #define CONFIG_ENV_SPI_MAX_HZ 15000000 242 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 243 "sf read 0x22000000 0x84000 0x294000; " \ 244 "bootm 0x22000000" 245 246 #elif CONFIG_SYS_USE_NANDFLASH 247 248 /* bootstrap + u-boot + env + linux in nandflash */ 249 #define CONFIG_ENV_OFFSET 0x120000 250 #define CONFIG_ENV_OFFSET_REDUND 0x100000 251 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 252 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 253 #endif 254 255 #define CONFIG_SYS_LONGHELP 1 256 #define CONFIG_CMDLINE_EDITING 1 257 #define CONFIG_AUTO_COMPLETE 258 259 /* 260 * Size of malloc() pool 261 */ 262 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 263 264 #endif 265