xref: /openbmc/u-boot/include/configs/at91sam9263ek.h (revision 8435179271106ec6fe9a9a5679b897755b1db8dd)
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9263EK board.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * SoC must be defined first, before hardware.h is included.
16  * In this case SoC is defined in boards.cfg.
17  */
18 #include <asm/hardware.h>
19 
20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
21 #define CONFIG_SYS_TEXT_BASE		0x21F00000
22 #else
23 #define CONFIG_SYS_TEXT_BASE		0x0000000
24 #endif
25 
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
28 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
29 
30 #define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
31 
32 #define CONFIG_ARCH_CPU_INIT
33 
34 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36 #define CONFIG_INITRD_TAG	1
37 
38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
39 #define CONFIG_SKIP_LOWLEVEL_INIT
40 #else
41 #define CONFIG_SYS_USE_NORFLASH
42 #endif
43 
44 #define CONFIG_BOARD_EARLY_INIT_F
45 
46 /*
47  * Hardware drivers
48  */
49 #define CONFIG_ATMEL_LEGACY
50 #define CONFIG_AT91_GPIO		1
51 #define CONFIG_AT91_GPIO_PULLUP		1
52 
53 /* serial console */
54 #define CONFIG_ATMEL_USART
55 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
56 #define CONFIG_USART_ID			ATMEL_ID_SYS
57 #define CONFIG_BAUDRATE			115200
58 
59 /* LCD */
60 #define CONFIG_LCD			1
61 #define LCD_BPP				LCD_COLOR8
62 #define CONFIG_LCD_LOGO			1
63 #undef LCD_TEST_PATTERN
64 #define CONFIG_LCD_INFO			1
65 #define CONFIG_LCD_INFO_BELOW_LOGO	1
66 #define CONFIG_SYS_WHITE_ON_BLACK	1
67 #define CONFIG_ATMEL_LCD		1
68 #define CONFIG_ATMEL_LCD_BGR555		1
69 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
70 
71 /* LED */
72 #define CONFIG_AT91_LED
73 #define	CONFIG_RED_LED		AT91_PIN_PB7	/* the power led */
74 #define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
75 #define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
76 
77 
78 /*
79  * BOOTP options
80  */
81 #define CONFIG_BOOTP_BOOTFILESIZE	1
82 #define CONFIG_BOOTP_BOOTPATH		1
83 #define CONFIG_BOOTP_GATEWAY		1
84 #define CONFIG_BOOTP_HOSTNAME		1
85 
86 /*
87  * Command line configuration.
88  */
89 #define CONFIG_CMD_NAND		1
90 
91 /* SDRAM */
92 #define CONFIG_NR_DRAM_BANKS		1
93 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
94 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
95 
96 #define CONFIG_SYS_INIT_SP_ADDR \
97 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
98 
99 /* DataFlash */
100 #define CONFIG_ATMEL_DATAFLASH_SPI
101 #define CONFIG_HAS_DATAFLASH		1
102 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
103 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
104 #define AT91_SPI_CLK			15000000
105 #define DATAFLASH_TCSS			(0x1a << 16)
106 #define DATAFLASH_TCHS			(0x1 << 24)
107 
108 /* MMC */
109 #ifdef CONFIG_CMD_MMC
110 #define CONFIG_MMC
111 #define CONFIG_GENERIC_MMC
112 #define CONFIG_GENERIC_ATMEL_MCI
113 #endif
114 
115 /* NOR flash, if populated */
116 #ifdef CONFIG_SYS_USE_NORFLASH
117 #define CONFIG_SYS_FLASH_CFI			1
118 #define CONFIG_FLASH_CFI_DRIVER			1
119 #define PHYS_FLASH_1				0x10000000
120 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
121 #define CONFIG_SYS_MAX_FLASH_SECT		256
122 #define CONFIG_SYS_MAX_FLASH_BANKS		1
123 
124 #define CONFIG_SYS_MONITOR_SEC	1:0-3
125 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
126 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
127 #define CONFIG_ENV_IS_IN_FLASH	1
128 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
129 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
130 
131 /* Address and size of Primary Environment Sector */
132 #define CONFIG_ENV_SIZE		0x10000
133 
134 #define CONFIG_EXTRA_ENV_SETTINGS	\
135 	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
136 	"update=" \
137 		"protect off ${monitor_base} +${filesize};" \
138 		"erase ${monitor_base} +${filesize};" \
139 		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
140 		"protect on ${monitor_base} +${filesize}\0"
141 
142 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
143 #define MASTER_PLL_MUL		171
144 #define MASTER_PLL_DIV		14
145 #define MASTER_PLL_OUT		3
146 
147 /* clocks */
148 #define CONFIG_SYS_MOR_VAL						\
149 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
150 #define CONFIG_SYS_PLLAR_VAL					\
151 	(AT91_PMC_PLLAR_29 |					\
152 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
153 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
154 	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
155 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
156 
157 /* PCK/2 = MCK Master Clock from PLLA */
158 #define	CONFIG_SYS_MCKR1_VAL		\
159 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
160 	 AT91_PMC_MCKR_MDIV_2)
161 
162 /* PCK/2 = MCK Master Clock from PLLA */
163 #define	CONFIG_SYS_MCKR2_VAL		\
164 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
165 	AT91_PMC_MCKR_MDIV_2)
166 
167 /* define PDC[31:16] as DATA[31:16] */
168 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
169 /* no pull-up for D[31:16] */
170 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
171 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
172 #define CONFIG_SYS_MATRIX_EBICSA_VAL					\
173 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
174 	 AT91_MATRIX_CSA_EBI_CS1A)
175 
176 /* SDRAM */
177 /* SDRAMC_MR Mode register */
178 #define CONFIG_SYS_SDRC_MR_VAL1		0
179 /* SDRAMC_TR - Refresh Timer register */
180 #define CONFIG_SYS_SDRC_TR_VAL1		0x13C
181 /* SDRAMC_CR - Configuration register*/
182 #define CONFIG_SYS_SDRC_CR_VAL							\
183 		(AT91_SDRAMC_NC_9 |						\
184 		 AT91_SDRAMC_NR_13 |						\
185 		 AT91_SDRAMC_NB_4 |						\
186 		 AT91_SDRAMC_CAS_3 |						\
187 		 AT91_SDRAMC_DBW_32 |						\
188 		 (1 <<  8) |		/* Write Recovery Delay */		\
189 		 (7 << 12) |		/* Row Cycle Delay */			\
190 		 (2 << 16) |		/* Row Precharge Delay */		\
191 		 (2 << 20) |		/* Row to Column Delay */		\
192 		 (5 << 24) |		/* Active to Precharge Delay */		\
193 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
194 
195 /* Memory Device Register -> SDRAM */
196 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
197 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
198 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
199 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
200 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
201 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
202 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
203 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
204 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
205 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
206 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
207 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
208 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
209 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
210 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
211 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
212 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
213 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
214 
215 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
216 #define CONFIG_SYS_SMC0_SETUP0_VAL				\
217 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
218 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
219 #define CONFIG_SYS_SMC0_PULSE0_VAL				\
220 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
221 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
222 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
223 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
224 #define CONFIG_SYS_SMC0_MODE0_VAL				\
225 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
226 	 AT91_SMC_MODE_DBW_16 |					\
227 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
228 
229 /* user reset enable */
230 #define CONFIG_SYS_RSTC_RMR_VAL			\
231 		(AT91_RSTC_KEY |		\
232 		AT91_RSTC_MR_URSTEN |		\
233 		AT91_RSTC_MR_ERSTL(15))
234 
235 /* Disable Watchdog */
236 #define CONFIG_SYS_WDTC_WDMR_VAL				\
237 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
238 		 AT91_WDT_MR_WDV(0xfff) |			\
239 		 AT91_WDT_MR_WDDIS |				\
240 		 AT91_WDT_MR_WDD(0xfff))
241 
242 #endif
243 
244 #else
245 #define CONFIG_SYS_NO_FLASH			1
246 #endif
247 
248 /* NAND flash */
249 #ifdef CONFIG_CMD_NAND
250 #define CONFIG_NAND_ATMEL
251 #define CONFIG_SYS_MAX_NAND_DEVICE		1
252 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
253 #define CONFIG_SYS_NAND_DBW_8			1
254 /* our ALE is AD21 */
255 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
256 /* our CLE is AD22 */
257 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
258 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
259 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
260 #endif
261 
262 /* Ethernet */
263 #define CONFIG_MACB			1
264 #define CONFIG_RMII			1
265 #define CONFIG_NET_RETRY_COUNT		20
266 #define CONFIG_RESET_PHY_R		1
267 #define CONFIG_AT91_WANTS_COMMON_PHY
268 
269 /* USB */
270 #define CONFIG_USB_ATMEL
271 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
272 #define CONFIG_USB_OHCI_NEW		1
273 #define CONFIG_DOS_PARTITION		1
274 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
275 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
276 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
277 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
278 
279 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
280 
281 #define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
282 #define CONFIG_SYS_MEMTEST_END			0x23e00000
283 
284 #ifdef CONFIG_SYS_USE_DATAFLASH
285 
286 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
287 #define CONFIG_ENV_IS_IN_DATAFLASH	1
288 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
289 #define CONFIG_ENV_OFFSET		0x4200
290 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
291 #define CONFIG_ENV_SIZE		0x4200
292 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
293 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
294 				"root=/dev/mtdblock0 " \
295 				"mtdparts=atmel_nand:-(root) "\
296 				"rw rootfstype=jffs2"
297 
298 #elif CONFIG_SYS_USE_NANDFLASH
299 
300 /* bootstrap + u-boot + env + linux in nandflash */
301 #define CONFIG_ENV_IS_IN_NAND		1
302 #define CONFIG_ENV_OFFSET		0xc0000
303 #define CONFIG_ENV_OFFSET_REDUND	0x100000
304 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
305 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
306 #define CONFIG_BOOTARGS							\
307 	"console=ttyS0,115200 earlyprintk "				\
308 	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
309 	"256k(env),256k(env_redundant),256k(spare),"			\
310 	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
311 	"root=/dev/mtdblock7 rw rootfstype=jffs2"
312 #endif
313 
314 #define CONFIG_SYS_CBSIZE		256
315 #define CONFIG_SYS_MAXARGS		16
316 #define CONFIG_SYS_LONGHELP		1
317 #define CONFIG_CMDLINE_EDITING		1
318 #define CONFIG_AUTO_COMPLETE
319 
320 /*
321  * Size of malloc() pool
322  */
323 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
324 
325 #endif
326