1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 #define CONFIG_BOARD_EARLY_INIT_F 45 46 #define CONFIG_DISPLAY_CPUINFO 47 48 #define CONFIG_CMD_BOOTZ 49 #define CONFIG_OF_LIBFDT 50 51 52 /* 53 * Hardware drivers 54 */ 55 #define CONFIG_ATMEL_LEGACY 56 #define CONFIG_AT91_GPIO 1 57 #define CONFIG_AT91_GPIO_PULLUP 1 58 59 /* serial console */ 60 #define CONFIG_ATMEL_USART 61 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 62 #define CONFIG_USART_ID ATMEL_ID_SYS 63 #define CONFIG_BAUDRATE 115200 64 65 /* LCD */ 66 #define CONFIG_LCD 1 67 #define LCD_BPP LCD_COLOR8 68 #define CONFIG_LCD_LOGO 1 69 #undef LCD_TEST_PATTERN 70 #define CONFIG_LCD_INFO 1 71 #define CONFIG_LCD_INFO_BELOW_LOGO 1 72 #define CONFIG_SYS_WHITE_ON_BLACK 1 73 #define CONFIG_ATMEL_LCD 1 74 #define CONFIG_ATMEL_LCD_BGR555 1 75 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 76 77 /* LED */ 78 #define CONFIG_AT91_LED 79 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 80 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 81 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 82 83 #define CONFIG_BOOTDELAY 3 84 85 /* 86 * BOOTP options 87 */ 88 #define CONFIG_BOOTP_BOOTFILESIZE 1 89 #define CONFIG_BOOTP_BOOTPATH 1 90 #define CONFIG_BOOTP_GATEWAY 1 91 #define CONFIG_BOOTP_HOSTNAME 1 92 93 /* 94 * Command line configuration. 95 */ 96 #define CONFIG_CMD_PING 1 97 #define CONFIG_CMD_DHCP 1 98 #define CONFIG_CMD_NAND 1 99 #define CONFIG_CMD_MMC 100 #define CONFIG_CMD_USB 1 101 102 /* SDRAM */ 103 #define CONFIG_NR_DRAM_BANKS 1 104 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 105 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 106 107 #define CONFIG_SYS_INIT_SP_ADDR \ 108 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 109 110 /* DataFlash */ 111 #define CONFIG_ATMEL_DATAFLASH_SPI 112 #define CONFIG_HAS_DATAFLASH 1 113 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 114 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 115 #define AT91_SPI_CLK 15000000 116 #define DATAFLASH_TCSS (0x1a << 16) 117 #define DATAFLASH_TCHS (0x1 << 24) 118 119 /* MMC */ 120 #ifdef CONFIG_CMD_MMC 121 #define CONFIG_MMC 122 #define CONFIG_GENERIC_MMC 123 #define CONFIG_GENERIC_ATMEL_MCI 124 #endif 125 126 /* FAT */ 127 #ifdef CONFIG_CMD_FAT 128 #define CONFIG_DOS_PARTITION 129 #endif 130 131 /* NOR flash, if populated */ 132 #ifdef CONFIG_SYS_USE_NORFLASH 133 #define CONFIG_SYS_FLASH_CFI 1 134 #define CONFIG_FLASH_CFI_DRIVER 1 135 #define PHYS_FLASH_1 0x10000000 136 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 137 #define CONFIG_SYS_MAX_FLASH_SECT 256 138 #define CONFIG_SYS_MAX_FLASH_BANKS 1 139 140 #define CONFIG_SYS_MONITOR_SEC 1:0-3 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 142 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 143 #define CONFIG_ENV_IS_IN_FLASH 1 144 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 145 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 146 147 /* Address and size of Primary Environment Sector */ 148 #define CONFIG_ENV_SIZE 0x10000 149 150 #define CONFIG_EXTRA_ENV_SETTINGS \ 151 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 152 "update=" \ 153 "protect off ${monitor_base} +${filesize};" \ 154 "erase ${monitor_base} +${filesize};" \ 155 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 156 "protect on ${monitor_base} +${filesize}\0" 157 158 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 159 #define MASTER_PLL_MUL 171 160 #define MASTER_PLL_DIV 14 161 #define MASTER_PLL_OUT 3 162 163 /* clocks */ 164 #define CONFIG_SYS_MOR_VAL \ 165 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 166 #define CONFIG_SYS_PLLAR_VAL \ 167 (AT91_PMC_PLLAR_29 | \ 168 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 169 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 170 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 171 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 172 173 /* PCK/2 = MCK Master Clock from PLLA */ 174 #define CONFIG_SYS_MCKR1_VAL \ 175 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 176 AT91_PMC_MCKR_MDIV_2) 177 178 /* PCK/2 = MCK Master Clock from PLLA */ 179 #define CONFIG_SYS_MCKR2_VAL \ 180 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 181 AT91_PMC_MCKR_MDIV_2) 182 183 /* define PDC[31:16] as DATA[31:16] */ 184 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 185 /* no pull-up for D[31:16] */ 186 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 187 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 188 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 189 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 190 AT91_MATRIX_CSA_EBI_CS1A) 191 192 /* SDRAM */ 193 /* SDRAMC_MR Mode register */ 194 #define CONFIG_SYS_SDRC_MR_VAL1 0 195 /* SDRAMC_TR - Refresh Timer register */ 196 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 197 /* SDRAMC_CR - Configuration register*/ 198 #define CONFIG_SYS_SDRC_CR_VAL \ 199 (AT91_SDRAMC_NC_9 | \ 200 AT91_SDRAMC_NR_13 | \ 201 AT91_SDRAMC_NB_4 | \ 202 AT91_SDRAMC_CAS_3 | \ 203 AT91_SDRAMC_DBW_32 | \ 204 (1 << 8) | /* Write Recovery Delay */ \ 205 (7 << 12) | /* Row Cycle Delay */ \ 206 (2 << 16) | /* Row Precharge Delay */ \ 207 (2 << 20) | /* Row to Column Delay */ \ 208 (5 << 24) | /* Active to Precharge Delay */ \ 209 (1 << 28)) /* Exit Self Refresh to Active Delay */ 210 211 /* Memory Device Register -> SDRAM */ 212 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 213 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 214 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 215 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 216 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 217 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 218 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 219 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 220 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 221 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 222 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 223 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 224 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 225 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 226 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 227 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 228 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 229 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 230 231 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 232 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 233 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 234 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 235 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 236 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 237 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 238 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 239 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 240 #define CONFIG_SYS_SMC0_MODE0_VAL \ 241 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 242 AT91_SMC_MODE_DBW_16 | \ 243 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 244 245 /* user reset enable */ 246 #define CONFIG_SYS_RSTC_RMR_VAL \ 247 (AT91_RSTC_KEY | \ 248 AT91_RSTC_MR_URSTEN | \ 249 AT91_RSTC_MR_ERSTL(15)) 250 251 /* Disable Watchdog */ 252 #define CONFIG_SYS_WDTC_WDMR_VAL \ 253 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 254 AT91_WDT_MR_WDV(0xfff) | \ 255 AT91_WDT_MR_WDDIS | \ 256 AT91_WDT_MR_WDD(0xfff)) 257 258 #endif 259 260 #else 261 #define CONFIG_SYS_NO_FLASH 1 262 #endif 263 264 /* NAND flash */ 265 #ifdef CONFIG_CMD_NAND 266 #define CONFIG_NAND_ATMEL 267 #define CONFIG_SYS_MAX_NAND_DEVICE 1 268 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 269 #define CONFIG_SYS_NAND_DBW_8 1 270 /* our ALE is AD21 */ 271 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 272 /* our CLE is AD22 */ 273 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 274 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 275 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 276 #endif 277 278 /* Ethernet */ 279 #define CONFIG_MACB 1 280 #define CONFIG_RMII 1 281 #define CONFIG_NET_RETRY_COUNT 20 282 #define CONFIG_RESET_PHY_R 1 283 #define CONFIG_AT91_WANTS_COMMON_PHY 284 285 /* USB */ 286 #define CONFIG_USB_ATMEL 287 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 288 #define CONFIG_USB_OHCI_NEW 1 289 #define CONFIG_DOS_PARTITION 1 290 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 291 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 292 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 293 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 294 #define CONFIG_USB_STORAGE 1 295 #define CONFIG_CMD_FAT 1 296 297 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 298 299 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 300 #define CONFIG_SYS_MEMTEST_END 0x23e00000 301 302 #ifdef CONFIG_SYS_USE_DATAFLASH 303 304 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 305 #define CONFIG_ENV_IS_IN_DATAFLASH 1 306 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 307 #define CONFIG_ENV_OFFSET 0x4200 308 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 309 #define CONFIG_ENV_SIZE 0x4200 310 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 311 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 312 "root=/dev/mtdblock0 " \ 313 "mtdparts=atmel_nand:-(root) "\ 314 "rw rootfstype=jffs2" 315 316 #elif CONFIG_SYS_USE_NANDFLASH 317 318 /* bootstrap + u-boot + env + linux in nandflash */ 319 #define CONFIG_ENV_IS_IN_NAND 1 320 #define CONFIG_ENV_OFFSET 0xc0000 321 #define CONFIG_ENV_OFFSET_REDUND 0x100000 322 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 323 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 324 #define CONFIG_BOOTARGS \ 325 "console=ttyS0,115200 earlyprintk " \ 326 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 327 "256k(env),256k(env_redundant),256k(spare)," \ 328 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 329 "root=/dev/mtdblock7 rw rootfstype=jffs2" 330 #endif 331 332 #define CONFIG_SYS_CBSIZE 256 333 #define CONFIG_SYS_MAXARGS 16 334 #define CONFIG_SYS_LONGHELP 1 335 #define CONFIG_CMDLINE_EDITING 1 336 #define CONFIG_AUTO_COMPLETE 337 #define CONFIG_SYS_HUSH_PARSER 338 339 /* 340 * Size of malloc() pool 341 */ 342 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 343 344 #endif 345