1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 /* ARM asynchronous clock */ 21 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 22 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 23 24 #define CONFIG_ARCH_CPU_INIT 25 26 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 1 28 #define CONFIG_INITRD_TAG 1 29 30 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 31 #define CONFIG_SKIP_LOWLEVEL_INIT 32 #else 33 #define CONFIG_SYS_USE_NORFLASH 34 #endif 35 36 /* 37 * Hardware drivers 38 */ 39 #define CONFIG_ATMEL_LEGACY 40 41 /* LCD */ 42 #define LCD_BPP LCD_COLOR8 43 #define CONFIG_LCD_LOGO 1 44 #undef LCD_TEST_PATTERN 45 #define CONFIG_LCD_INFO 1 46 #define CONFIG_LCD_INFO_BELOW_LOGO 1 47 #define CONFIG_ATMEL_LCD 1 48 #define CONFIG_ATMEL_LCD_BGR555 1 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_BOOTFILESIZE 1 54 55 /* SDRAM */ 56 #define CONFIG_NR_DRAM_BANKS 1 57 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 58 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 59 60 #define CONFIG_SYS_INIT_SP_ADDR \ 61 (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 62 63 /* NOR flash, if populated */ 64 #ifdef CONFIG_SYS_USE_NORFLASH 65 #define CONFIG_SYS_FLASH_CFI 1 66 #define CONFIG_FLASH_CFI_DRIVER 1 67 #define PHYS_FLASH_1 0x10000000 68 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 69 #define CONFIG_SYS_MAX_FLASH_SECT 256 70 #define CONFIG_SYS_MAX_FLASH_BANKS 1 71 72 #define CONFIG_SYS_MONITOR_SEC 1:0-3 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 74 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 75 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 76 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 77 78 /* Address and size of Primary Environment Sector */ 79 #define CONFIG_ENV_SIZE 0x10000 80 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 83 "update=" \ 84 "protect off ${monitor_base} +${filesize};" \ 85 "erase ${monitor_base} +${filesize};" \ 86 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 87 "protect on ${monitor_base} +${filesize}\0" 88 89 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 90 #define MASTER_PLL_MUL 171 91 #define MASTER_PLL_DIV 14 92 #define MASTER_PLL_OUT 3 93 94 /* clocks */ 95 #define CONFIG_SYS_MOR_VAL \ 96 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 97 #define CONFIG_SYS_PLLAR_VAL \ 98 (AT91_PMC_PLLAR_29 | \ 99 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 100 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 101 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 102 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 103 104 /* PCK/2 = MCK Master Clock from PLLA */ 105 #define CONFIG_SYS_MCKR1_VAL \ 106 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 107 AT91_PMC_MCKR_MDIV_2) 108 109 /* PCK/2 = MCK Master Clock from PLLA */ 110 #define CONFIG_SYS_MCKR2_VAL \ 111 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 112 AT91_PMC_MCKR_MDIV_2) 113 114 /* define PDC[31:16] as DATA[31:16] */ 115 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 116 /* no pull-up for D[31:16] */ 117 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 118 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 119 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 120 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 121 AT91_MATRIX_CSA_EBI_CS1A) 122 123 /* SDRAM */ 124 /* SDRAMC_MR Mode register */ 125 #define CONFIG_SYS_SDRC_MR_VAL1 0 126 /* SDRAMC_TR - Refresh Timer register */ 127 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 128 /* SDRAMC_CR - Configuration register*/ 129 #define CONFIG_SYS_SDRC_CR_VAL \ 130 (AT91_SDRAMC_NC_9 | \ 131 AT91_SDRAMC_NR_13 | \ 132 AT91_SDRAMC_NB_4 | \ 133 AT91_SDRAMC_CAS_3 | \ 134 AT91_SDRAMC_DBW_32 | \ 135 (1 << 8) | /* Write Recovery Delay */ \ 136 (7 << 12) | /* Row Cycle Delay */ \ 137 (2 << 16) | /* Row Precharge Delay */ \ 138 (2 << 20) | /* Row to Column Delay */ \ 139 (5 << 24) | /* Active to Precharge Delay */ \ 140 (1 << 28)) /* Exit Self Refresh to Active Delay */ 141 142 /* Memory Device Register -> SDRAM */ 143 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 144 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 145 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 146 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 147 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 148 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 149 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 150 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 151 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 152 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 153 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 154 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 155 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 156 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 157 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 158 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 159 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 160 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 161 162 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 163 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 164 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 165 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 166 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 167 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 168 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 169 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 170 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 171 #define CONFIG_SYS_SMC0_MODE0_VAL \ 172 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 173 AT91_SMC_MODE_DBW_16 | \ 174 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 175 176 /* user reset enable */ 177 #define CONFIG_SYS_RSTC_RMR_VAL \ 178 (AT91_RSTC_KEY | \ 179 AT91_RSTC_MR_URSTEN | \ 180 AT91_RSTC_MR_ERSTL(15)) 181 182 /* Disable Watchdog */ 183 #define CONFIG_SYS_WDTC_WDMR_VAL \ 184 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 185 AT91_WDT_MR_WDV(0xfff) | \ 186 AT91_WDT_MR_WDDIS | \ 187 AT91_WDT_MR_WDD(0xfff)) 188 189 #endif 190 #endif 191 192 /* NAND flash */ 193 #ifdef CONFIG_CMD_NAND 194 #define CONFIG_NAND_ATMEL 195 #define CONFIG_SYS_MAX_NAND_DEVICE 1 196 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 197 #define CONFIG_SYS_NAND_DBW_8 1 198 /* our ALE is AD21 */ 199 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 200 /* our CLE is AD22 */ 201 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 202 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 203 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 204 #endif 205 206 /* Ethernet */ 207 #define CONFIG_RESET_PHY_R 1 208 #define CONFIG_AT91_WANTS_COMMON_PHY 209 210 /* USB */ 211 #define CONFIG_USB_ATMEL 212 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 213 #define CONFIG_USB_OHCI_NEW 1 214 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 215 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 216 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 217 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 218 219 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 220 221 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 222 #define CONFIG_SYS_MEMTEST_END 0x23e00000 223 224 #ifdef CONFIG_SYS_USE_DATAFLASH 225 226 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 227 #define CONFIG_ENV_OFFSET 0x4200 228 #define CONFIG_ENV_SIZE 0x4200 229 #define CONFIG_ENV_SECT_SIZE 0x210 230 #define CONFIG_ENV_SPI_MAX_HZ 15000000 231 #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 232 "sf read 0x22000000 0x84000 0x294000; " \ 233 "bootm 0x22000000" 234 235 #elif CONFIG_SYS_USE_NANDFLASH 236 237 /* bootstrap + u-boot + env + linux in nandflash */ 238 #define CONFIG_ENV_OFFSET 0x120000 239 #define CONFIG_ENV_OFFSET_REDUND 0x100000 240 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 241 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 242 #endif 243 244 /* 245 * Size of malloc() pool 246 */ 247 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 248 249 #endif 250