1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 #define CONFIG_BOARD_EARLY_INIT_F 45 46 #define CONFIG_DISPLAY_CPUINFO 47 48 #define CONFIG_CMD_BOOTZ 49 50 /* 51 * Hardware drivers 52 */ 53 #define CONFIG_ATMEL_LEGACY 54 #define CONFIG_AT91_GPIO 1 55 #define CONFIG_AT91_GPIO_PULLUP 1 56 57 /* serial console */ 58 #define CONFIG_ATMEL_USART 59 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 60 #define CONFIG_USART_ID ATMEL_ID_SYS 61 #define CONFIG_BAUDRATE 115200 62 63 /* LCD */ 64 #define CONFIG_LCD 1 65 #define LCD_BPP LCD_COLOR8 66 #define CONFIG_LCD_LOGO 1 67 #undef LCD_TEST_PATTERN 68 #define CONFIG_LCD_INFO 1 69 #define CONFIG_LCD_INFO_BELOW_LOGO 1 70 #define CONFIG_SYS_WHITE_ON_BLACK 1 71 #define CONFIG_ATMEL_LCD 1 72 #define CONFIG_ATMEL_LCD_BGR555 1 73 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 74 75 /* LED */ 76 #define CONFIG_AT91_LED 77 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 78 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 79 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 80 81 #define CONFIG_BOOTDELAY 3 82 83 /* 84 * BOOTP options 85 */ 86 #define CONFIG_BOOTP_BOOTFILESIZE 1 87 #define CONFIG_BOOTP_BOOTPATH 1 88 #define CONFIG_BOOTP_GATEWAY 1 89 #define CONFIG_BOOTP_HOSTNAME 1 90 91 /* 92 * Command line configuration. 93 */ 94 #define CONFIG_CMD_PING 1 95 #define CONFIG_CMD_DHCP 1 96 #define CONFIG_CMD_NAND 1 97 #define CONFIG_CMD_MMC 98 #define CONFIG_CMD_USB 1 99 100 /* SDRAM */ 101 #define CONFIG_NR_DRAM_BANKS 1 102 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 103 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 104 105 #define CONFIG_SYS_INIT_SP_ADDR \ 106 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 107 108 /* DataFlash */ 109 #define CONFIG_ATMEL_DATAFLASH_SPI 110 #define CONFIG_HAS_DATAFLASH 1 111 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 112 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 113 #define AT91_SPI_CLK 15000000 114 #define DATAFLASH_TCSS (0x1a << 16) 115 #define DATAFLASH_TCHS (0x1 << 24) 116 117 /* MMC */ 118 #ifdef CONFIG_CMD_MMC 119 #define CONFIG_MMC 120 #define CONFIG_GENERIC_MMC 121 #define CONFIG_GENERIC_ATMEL_MCI 122 #endif 123 124 /* FAT */ 125 #ifdef CONFIG_CMD_FAT 126 #define CONFIG_DOS_PARTITION 127 #endif 128 129 /* NOR flash, if populated */ 130 #ifdef CONFIG_SYS_USE_NORFLASH 131 #define CONFIG_SYS_FLASH_CFI 1 132 #define CONFIG_FLASH_CFI_DRIVER 1 133 #define PHYS_FLASH_1 0x10000000 134 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 135 #define CONFIG_SYS_MAX_FLASH_SECT 256 136 #define CONFIG_SYS_MAX_FLASH_BANKS 1 137 138 #define CONFIG_SYS_MONITOR_SEC 1:0-3 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 140 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 141 #define CONFIG_ENV_IS_IN_FLASH 1 142 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 143 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 144 145 /* Address and size of Primary Environment Sector */ 146 #define CONFIG_ENV_SIZE 0x10000 147 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 150 "update=" \ 151 "protect off ${monitor_base} +${filesize};" \ 152 "erase ${monitor_base} +${filesize};" \ 153 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 154 "protect on ${monitor_base} +${filesize}\0" 155 156 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 157 #define MASTER_PLL_MUL 171 158 #define MASTER_PLL_DIV 14 159 #define MASTER_PLL_OUT 3 160 161 /* clocks */ 162 #define CONFIG_SYS_MOR_VAL \ 163 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 164 #define CONFIG_SYS_PLLAR_VAL \ 165 (AT91_PMC_PLLAR_29 | \ 166 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 167 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 168 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 169 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 170 171 /* PCK/2 = MCK Master Clock from PLLA */ 172 #define CONFIG_SYS_MCKR1_VAL \ 173 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 174 AT91_PMC_MCKR_MDIV_2) 175 176 /* PCK/2 = MCK Master Clock from PLLA */ 177 #define CONFIG_SYS_MCKR2_VAL \ 178 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 179 AT91_PMC_MCKR_MDIV_2) 180 181 /* define PDC[31:16] as DATA[31:16] */ 182 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 183 /* no pull-up for D[31:16] */ 184 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 185 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 186 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 187 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 188 AT91_MATRIX_CSA_EBI_CS1A) 189 190 /* SDRAM */ 191 /* SDRAMC_MR Mode register */ 192 #define CONFIG_SYS_SDRC_MR_VAL1 0 193 /* SDRAMC_TR - Refresh Timer register */ 194 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 195 /* SDRAMC_CR - Configuration register*/ 196 #define CONFIG_SYS_SDRC_CR_VAL \ 197 (AT91_SDRAMC_NC_9 | \ 198 AT91_SDRAMC_NR_13 | \ 199 AT91_SDRAMC_NB_4 | \ 200 AT91_SDRAMC_CAS_3 | \ 201 AT91_SDRAMC_DBW_32 | \ 202 (1 << 8) | /* Write Recovery Delay */ \ 203 (7 << 12) | /* Row Cycle Delay */ \ 204 (2 << 16) | /* Row Precharge Delay */ \ 205 (2 << 20) | /* Row to Column Delay */ \ 206 (5 << 24) | /* Active to Precharge Delay */ \ 207 (1 << 28)) /* Exit Self Refresh to Active Delay */ 208 209 /* Memory Device Register -> SDRAM */ 210 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 211 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 212 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 213 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 214 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 215 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 216 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 217 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 218 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 219 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 220 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 221 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 222 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 223 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 224 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 225 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 226 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 227 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 228 229 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 230 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 231 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 232 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 233 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 234 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 235 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 236 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 237 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 238 #define CONFIG_SYS_SMC0_MODE0_VAL \ 239 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 240 AT91_SMC_MODE_DBW_16 | \ 241 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 242 243 /* user reset enable */ 244 #define CONFIG_SYS_RSTC_RMR_VAL \ 245 (AT91_RSTC_KEY | \ 246 AT91_RSTC_MR_URSTEN | \ 247 AT91_RSTC_MR_ERSTL(15)) 248 249 /* Disable Watchdog */ 250 #define CONFIG_SYS_WDTC_WDMR_VAL \ 251 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 252 AT91_WDT_MR_WDV(0xfff) | \ 253 AT91_WDT_MR_WDDIS | \ 254 AT91_WDT_MR_WDD(0xfff)) 255 256 #endif 257 258 #else 259 #define CONFIG_SYS_NO_FLASH 1 260 #endif 261 262 /* NAND flash */ 263 #ifdef CONFIG_CMD_NAND 264 #define CONFIG_NAND_ATMEL 265 #define CONFIG_SYS_MAX_NAND_DEVICE 1 266 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 267 #define CONFIG_SYS_NAND_DBW_8 1 268 /* our ALE is AD21 */ 269 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 270 /* our CLE is AD22 */ 271 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 272 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 273 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 274 #endif 275 276 /* Ethernet */ 277 #define CONFIG_MACB 1 278 #define CONFIG_RMII 1 279 #define CONFIG_NET_RETRY_COUNT 20 280 #define CONFIG_RESET_PHY_R 1 281 #define CONFIG_AT91_WANTS_COMMON_PHY 282 283 /* USB */ 284 #define CONFIG_USB_ATMEL 285 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 286 #define CONFIG_USB_OHCI_NEW 1 287 #define CONFIG_DOS_PARTITION 1 288 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 289 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 290 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 291 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 292 #define CONFIG_USB_STORAGE 1 293 #define CONFIG_CMD_FAT 1 294 295 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 296 297 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 298 #define CONFIG_SYS_MEMTEST_END 0x23e00000 299 300 #ifdef CONFIG_SYS_USE_DATAFLASH 301 302 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 303 #define CONFIG_ENV_IS_IN_DATAFLASH 1 304 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 305 #define CONFIG_ENV_OFFSET 0x4200 306 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 307 #define CONFIG_ENV_SIZE 0x4200 308 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 309 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 310 "root=/dev/mtdblock0 " \ 311 "mtdparts=atmel_nand:-(root) "\ 312 "rw rootfstype=jffs2" 313 314 #elif CONFIG_SYS_USE_NANDFLASH 315 316 /* bootstrap + u-boot + env + linux in nandflash */ 317 #define CONFIG_ENV_IS_IN_NAND 1 318 #define CONFIG_ENV_OFFSET 0xc0000 319 #define CONFIG_ENV_OFFSET_REDUND 0x100000 320 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 321 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 322 #define CONFIG_BOOTARGS \ 323 "console=ttyS0,115200 earlyprintk " \ 324 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 325 "256k(env),256k(env_redundant),256k(spare)," \ 326 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 327 "root=/dev/mtdblock7 rw rootfstype=jffs2" 328 #endif 329 330 #define CONFIG_SYS_CBSIZE 256 331 #define CONFIG_SYS_MAXARGS 16 332 #define CONFIG_SYS_LONGHELP 1 333 #define CONFIG_CMDLINE_EDITING 1 334 #define CONFIG_AUTO_COMPLETE 335 #define CONFIG_SYS_HUSH_PARSER 336 337 /* 338 * Size of malloc() pool 339 */ 340 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 341 342 #endif 343