1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 #define CONFIG_SYS_HZ 1000 30 31 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 32 33 #define CONFIG_ARCH_CPU_INIT 34 35 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 36 #define CONFIG_SETUP_MEMORY_TAGS 1 37 #define CONFIG_INITRD_TAG 1 38 39 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 40 #define CONFIG_SKIP_LOWLEVEL_INIT 41 #else 42 #define CONFIG_SYS_USE_NORFLASH 43 #endif 44 45 #define CONFIG_BOARD_EARLY_INIT_F 46 47 #define CONFIG_DISPLAY_CPUINFO 48 49 #define CONFIG_CMD_BOOTZ 50 #define CONFIG_OF_LIBFDT 51 52 /* 53 * Hardware drivers 54 */ 55 #define CONFIG_ATMEL_LEGACY 56 #define CONFIG_AT91_GPIO 1 57 #define CONFIG_AT91_GPIO_PULLUP 1 58 59 /* serial console */ 60 #define CONFIG_ATMEL_USART 61 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 62 #define CONFIG_USART_ID ATMEL_ID_SYS 63 #define CONFIG_BAUDRATE 115200 64 65 /* LCD */ 66 #define CONFIG_LCD 1 67 #define LCD_BPP LCD_COLOR8 68 #define CONFIG_LCD_LOGO 1 69 #undef LCD_TEST_PATTERN 70 #define CONFIG_LCD_INFO 1 71 #define CONFIG_LCD_INFO_BELOW_LOGO 1 72 #define CONFIG_SYS_WHITE_ON_BLACK 1 73 #define CONFIG_ATMEL_LCD 1 74 #define CONFIG_ATMEL_LCD_BGR555 1 75 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 76 77 /* LED */ 78 #define CONFIG_AT91_LED 79 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 80 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 81 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 82 83 #define CONFIG_BOOTDELAY 3 84 85 /* 86 * BOOTP options 87 */ 88 #define CONFIG_BOOTP_BOOTFILESIZE 1 89 #define CONFIG_BOOTP_BOOTPATH 1 90 #define CONFIG_BOOTP_GATEWAY 1 91 #define CONFIG_BOOTP_HOSTNAME 1 92 93 /* 94 * Command line configuration. 95 */ 96 #include <config_cmd_default.h> 97 #undef CONFIG_CMD_BDI 98 #undef CONFIG_CMD_FPGA 99 #undef CONFIG_CMD_IMI 100 #undef CONFIG_CMD_IMLS 101 #undef CONFIG_CMD_LOADS 102 #undef CONFIG_CMD_SOURCE 103 104 #define CONFIG_CMD_PING 1 105 #define CONFIG_CMD_DHCP 1 106 #define CONFIG_CMD_NAND 1 107 #define CONFIG_CMD_USB 1 108 109 /* SDRAM */ 110 #define CONFIG_NR_DRAM_BANKS 1 111 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 112 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 113 114 #define CONFIG_SYS_INIT_SP_ADDR \ 115 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 116 117 /* DataFlash */ 118 #define CONFIG_ATMEL_DATAFLASH_SPI 119 #define CONFIG_HAS_DATAFLASH 1 120 #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 121 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 122 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 123 #define AT91_SPI_CLK 15000000 124 #define DATAFLASH_TCSS (0x1a << 16) 125 #define DATAFLASH_TCHS (0x1 << 24) 126 127 /* NOR flash, if populated */ 128 #ifdef CONFIG_SYS_USE_NORFLASH 129 #define CONFIG_SYS_FLASH_CFI 1 130 #define CONFIG_FLASH_CFI_DRIVER 1 131 #define PHYS_FLASH_1 0x10000000 132 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 133 #define CONFIG_SYS_MAX_FLASH_SECT 256 134 #define CONFIG_SYS_MAX_FLASH_BANKS 1 135 136 #define CONFIG_SYS_MONITOR_SEC 1:0-3 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 138 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 139 #define CONFIG_ENV_IS_IN_FLASH 1 140 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 141 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 142 143 /* Address and size of Primary Environment Sector */ 144 #define CONFIG_ENV_SIZE 0x10000 145 146 #define CONFIG_EXTRA_ENV_SETTINGS \ 147 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 148 "update=" \ 149 "protect off ${monitor_base} +${filesize};" \ 150 "erase ${monitor_base} +${filesize};" \ 151 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 152 "protect on ${monitor_base} +${filesize}\0" 153 154 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 155 #define MASTER_PLL_MUL 171 156 #define MASTER_PLL_DIV 14 157 #define MASTER_PLL_OUT 3 158 159 /* clocks */ 160 #define CONFIG_SYS_MOR_VAL \ 161 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 162 #define CONFIG_SYS_PLLAR_VAL \ 163 (AT91_PMC_PLLAR_29 | \ 164 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 165 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 166 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 167 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 168 169 /* PCK/2 = MCK Master Clock from PLLA */ 170 #define CONFIG_SYS_MCKR1_VAL \ 171 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 172 AT91_PMC_MCKR_MDIV_2) 173 174 /* PCK/2 = MCK Master Clock from PLLA */ 175 #define CONFIG_SYS_MCKR2_VAL \ 176 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 177 AT91_PMC_MCKR_MDIV_2) 178 179 /* define PDC[31:16] as DATA[31:16] */ 180 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 181 /* no pull-up for D[31:16] */ 182 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 183 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 184 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 185 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 186 AT91_MATRIX_CSA_EBI_CS1A) 187 188 /* SDRAM */ 189 /* SDRAMC_MR Mode register */ 190 #define CONFIG_SYS_SDRC_MR_VAL1 0 191 /* SDRAMC_TR - Refresh Timer register */ 192 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 193 /* SDRAMC_CR - Configuration register*/ 194 #define CONFIG_SYS_SDRC_CR_VAL \ 195 (AT91_SDRAMC_NC_9 | \ 196 AT91_SDRAMC_NR_13 | \ 197 AT91_SDRAMC_NB_4 | \ 198 AT91_SDRAMC_CAS_3 | \ 199 AT91_SDRAMC_DBW_32 | \ 200 (1 << 8) | /* Write Recovery Delay */ \ 201 (7 << 12) | /* Row Cycle Delay */ \ 202 (2 << 16) | /* Row Precharge Delay */ \ 203 (2 << 20) | /* Row to Column Delay */ \ 204 (5 << 24) | /* Active to Precharge Delay */ \ 205 (1 << 28)) /* Exit Self Refresh to Active Delay */ 206 207 /* Memory Device Register -> SDRAM */ 208 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 209 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 210 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 211 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 212 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 213 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 214 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 215 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 216 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 217 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 218 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 219 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 220 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 221 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 222 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 223 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 224 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 225 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 226 227 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 228 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 229 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 230 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 231 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 232 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 233 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 234 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 235 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 236 #define CONFIG_SYS_SMC0_MODE0_VAL \ 237 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 238 AT91_SMC_MODE_DBW_16 | \ 239 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 240 241 /* user reset enable */ 242 #define CONFIG_SYS_RSTC_RMR_VAL \ 243 (AT91_RSTC_KEY | \ 244 AT91_RSTC_MR_URSTEN | \ 245 AT91_RSTC_MR_ERSTL(15)) 246 247 /* Disable Watchdog */ 248 #define CONFIG_SYS_WDTC_WDMR_VAL \ 249 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 250 AT91_WDT_MR_WDV(0xfff) | \ 251 AT91_WDT_MR_WDDIS | \ 252 AT91_WDT_MR_WDD(0xfff)) 253 254 #endif 255 256 #else 257 #define CONFIG_SYS_NO_FLASH 1 258 #endif 259 260 /* NAND flash */ 261 #ifdef CONFIG_CMD_NAND 262 #define CONFIG_NAND_ATMEL 263 #define CONFIG_SYS_MAX_NAND_DEVICE 1 264 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 265 #define CONFIG_SYS_NAND_DBW_8 1 266 /* our ALE is AD21 */ 267 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 268 /* our CLE is AD22 */ 269 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 270 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 271 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 272 #endif 273 274 /* Ethernet */ 275 #define CONFIG_MACB 1 276 #define CONFIG_RMII 1 277 #define CONFIG_NET_RETRY_COUNT 20 278 #define CONFIG_RESET_PHY_R 1 279 280 /* USB */ 281 #define CONFIG_USB_ATMEL 282 #define CONFIG_USB_OHCI_NEW 1 283 #define CONFIG_DOS_PARTITION 1 284 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 285 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 286 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 287 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 288 #define CONFIG_USB_STORAGE 1 289 #define CONFIG_CMD_FAT 1 290 291 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 292 293 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 294 #define CONFIG_SYS_MEMTEST_END 0x23e00000 295 296 #ifdef CONFIG_SYS_USE_DATAFLASH 297 298 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 299 #define CONFIG_ENV_IS_IN_DATAFLASH 1 300 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 301 #define CONFIG_ENV_OFFSET 0x4200 302 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 303 #define CONFIG_ENV_SIZE 0x4200 304 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 305 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 306 "root=/dev/mtdblock0 " \ 307 "mtdparts=atmel_nand:-(root) "\ 308 "rw rootfstype=jffs2" 309 310 #elif CONFIG_SYS_USE_NANDFLASH 311 312 /* bootstrap + u-boot + env + linux in nandflash */ 313 #define CONFIG_ENV_IS_IN_NAND 1 314 #define CONFIG_ENV_OFFSET 0xc0000 315 #define CONFIG_ENV_OFFSET_REDUND 0x100000 316 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 317 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 318 #define CONFIG_BOOTARGS \ 319 "console=ttyS0,115200 earlyprintk " \ 320 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 321 "256k(env),256k(env_redundant),256k(spare)," \ 322 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 323 "root=/dev/mtdblock7 rw rootfstype=jffs2" 324 #endif 325 326 #define CONFIG_SYS_PROMPT "U-Boot> " 327 #define CONFIG_SYS_CBSIZE 256 328 #define CONFIG_SYS_MAXARGS 16 329 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 330 #define CONFIG_SYS_LONGHELP 1 331 #define CONFIG_CMDLINE_EDITING 1 332 #define CONFIG_AUTO_COMPLETE 333 #define CONFIG_SYS_HUSH_PARSER 334 335 /* 336 * Size of malloc() pool 337 */ 338 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 339 340 #endif 341