1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9263EK board.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29 
30 /*
31  * SoC must be defined first, before hardware.h is included.
32  * In this case SoC is defined in boards.cfg.
33  */
34 #include <asm/hardware.h>
35 
36 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
37 #define CONFIG_SYS_TEXT_BASE		0x21F00000
38 #else
39 #define CONFIG_SYS_TEXT_BASE		0x0000000
40 #endif
41 
42 /* ARM asynchronous clock */
43 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
44 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
45 #define CONFIG_SYS_HZ			1000
46 
47 #define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
48 
49 #define CONFIG_ARCH_CPU_INIT
50 
51 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
52 #define CONFIG_SETUP_MEMORY_TAGS 1
53 #define CONFIG_INITRD_TAG	1
54 
55 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
56 #define CONFIG_SKIP_LOWLEVEL_INIT
57 #else
58 #define CONFIG_SYS_USE_NORFLASH
59 #endif
60 
61 #define CONFIG_BOARD_EARLY_INIT_F
62 
63 #define CONFIG_DISPLAY_CPUINFO
64 
65 /*
66  * Hardware drivers
67  */
68 #define CONFIG_ATMEL_LEGACY
69 #define CONFIG_AT91_GPIO		1
70 #define CONFIG_AT91_GPIO_PULLUP		1
71 
72 /* serial console */
73 #define CONFIG_ATMEL_USART
74 #define CONFIG_USART_BASE		ATMEL_BASE_DBGU
75 #define CONFIG_USART_ID			ATMEL_ID_SYS
76 #define CONFIG_BAUDRATE			115200
77 
78 /* LCD */
79 #define CONFIG_LCD			1
80 #define LCD_BPP				LCD_COLOR8
81 #define CONFIG_LCD_LOGO			1
82 #undef LCD_TEST_PATTERN
83 #define CONFIG_LCD_INFO			1
84 #define CONFIG_LCD_INFO_BELOW_LOGO	1
85 #define CONFIG_SYS_WHITE_ON_BLACK	1
86 #define CONFIG_ATMEL_LCD		1
87 #define CONFIG_ATMEL_LCD_BGR555		1
88 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
89 
90 /* LED */
91 #define CONFIG_AT91_LED
92 #define	CONFIG_RED_LED		AT91_PIN_PB7	/* the power led */
93 #define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
94 #define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
95 
96 #define CONFIG_BOOTDELAY	3
97 
98 /*
99  * BOOTP options
100  */
101 #define CONFIG_BOOTP_BOOTFILESIZE	1
102 #define CONFIG_BOOTP_BOOTPATH		1
103 #define CONFIG_BOOTP_GATEWAY		1
104 #define CONFIG_BOOTP_HOSTNAME		1
105 
106 /*
107  * Command line configuration.
108  */
109 #include <config_cmd_default.h>
110 #undef CONFIG_CMD_BDI
111 #undef CONFIG_CMD_FPGA
112 #undef CONFIG_CMD_IMI
113 #undef CONFIG_CMD_IMLS
114 #undef CONFIG_CMD_LOADS
115 #undef CONFIG_CMD_SOURCE
116 
117 #define CONFIG_CMD_PING		1
118 #define CONFIG_CMD_DHCP		1
119 #define CONFIG_CMD_NAND		1
120 #define CONFIG_CMD_USB		1
121 
122 /* SDRAM */
123 #define CONFIG_NR_DRAM_BANKS		1
124 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
125 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
126 
127 #define CONFIG_SYS_INIT_SP_ADDR \
128 	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
129 
130 /* DataFlash */
131 #define CONFIG_ATMEL_DATAFLASH_SPI
132 #define CONFIG_HAS_DATAFLASH		1
133 #define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
134 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
135 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
136 #define AT91_SPI_CLK			15000000
137 #define DATAFLASH_TCSS			(0x1a << 16)
138 #define DATAFLASH_TCHS			(0x1 << 24)
139 
140 /* NOR flash, if populated */
141 #ifdef CONFIG_SYS_USE_NORFLASH
142 #define CONFIG_SYS_FLASH_CFI			1
143 #define CONFIG_FLASH_CFI_DRIVER			1
144 #define PHYS_FLASH_1				0x10000000
145 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
146 #define CONFIG_SYS_MAX_FLASH_SECT		256
147 #define CONFIG_SYS_MAX_FLASH_BANKS		1
148 
149 #define CONFIG_SYS_MONITOR_SEC	1:0-3
150 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
151 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
152 #define CONFIG_ENV_IS_IN_FLASH	1
153 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
154 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
155 
156 /* Address and size of Primary Environment Sector */
157 #define CONFIG_ENV_SIZE		0x10000
158 
159 #define xstr(s)   str(s)
160 #define str(s)	#s
161 
162 #define CONFIG_EXTRA_ENV_SETTINGS	\
163 	"monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
164 	"update=" \
165 		"protect off ${monitor_base} +${filesize};" \
166 		"erase ${monitor_base} +${filesize};" \
167 		"cp.b ${load_addr} ${monitor_base} ${filesize};" \
168 		"protect on ${monitor_base} +${filesize}\0"
169 
170 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
171 #define MASTER_PLL_MUL		171
172 #define MASTER_PLL_DIV		14
173 #define MASTER_PLL_OUT		3
174 
175 /* clocks */
176 #define CONFIG_SYS_MOR_VAL						\
177 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
178 #define CONFIG_SYS_PLLAR_VAL					\
179 	(AT91_PMC_PLLAR_29 |					\
180 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
181 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
182 	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
183 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
184 
185 /* PCK/2 = MCK Master Clock from PLLA */
186 #define	CONFIG_SYS_MCKR1_VAL		\
187 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
188 	 AT91_PMC_MCKR_MDIV_2)
189 
190 /* PCK/2 = MCK Master Clock from PLLA */
191 #define	CONFIG_SYS_MCKR2_VAL		\
192 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
193 	AT91_PMC_MCKR_MDIV_2)
194 
195 /* define PDC[31:16] as DATA[31:16] */
196 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
197 /* no pull-up for D[31:16] */
198 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
199 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
200 #define CONFIG_SYS_MATRIX_EBICSA_VAL					\
201 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
202 	 AT91_MATRIX_CSA_EBI_CS1A)
203 
204 /* SDRAM */
205 /* SDRAMC_MR Mode register */
206 #define CONFIG_SYS_SDRC_MR_VAL1		0
207 /* SDRAMC_TR - Refresh Timer register */
208 #define CONFIG_SYS_SDRC_TR_VAL1		0x13C
209 /* SDRAMC_CR - Configuration register*/
210 #define CONFIG_SYS_SDRC_CR_VAL							\
211 		(AT91_SDRAMC_NC_9 |						\
212 		 AT91_SDRAMC_NR_13 |						\
213 		 AT91_SDRAMC_NB_4 |						\
214 		 AT91_SDRAMC_CAS_3 |						\
215 		 AT91_SDRAMC_DBW_32 |						\
216 		 (1 <<  8) |		/* Write Recovery Delay */		\
217 		 (7 << 12) |		/* Row Cycle Delay */			\
218 		 (2 << 16) |		/* Row Precharge Delay */		\
219 		 (2 << 20) |		/* Row to Column Delay */		\
220 		 (5 << 24) |		/* Active to Precharge Delay */		\
221 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
222 
223 /* Memory Device Register -> SDRAM */
224 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
225 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
226 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
227 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
228 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
229 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
230 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
231 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
232 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
233 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
234 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
235 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
236 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
237 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
238 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
239 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
240 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
241 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
242 
243 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
244 #define CONFIG_SYS_SMC0_SETUP0_VAL				\
245 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
246 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
247 #define CONFIG_SYS_SMC0_PULSE0_VAL				\
248 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
249 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
250 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
251 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
252 #define CONFIG_SYS_SMC0_MODE0_VAL				\
253 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
254 	 AT91_SMC_MODE_DBW_16 |					\
255 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
256 
257 /* user reset enable */
258 #define CONFIG_SYS_RSTC_RMR_VAL			\
259 		(AT91_RSTC_KEY |		\
260 		AT91_RSTC_MR_URSTEN |		\
261 		AT91_RSTC_MR_ERSTL(15))
262 
263 /* Disable Watchdog */
264 #define CONFIG_SYS_WDTC_WDMR_VAL				\
265 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
266 		 AT91_WDT_MR_WDV(0xfff) |			\
267 		 AT91_WDT_MR_WDDIS |				\
268 		 AT91_WDT_MR_WDD(0xfff))
269 
270 #endif
271 
272 #else
273 #define CONFIG_SYS_NO_FLASH			1
274 #endif
275 
276 /* NAND flash */
277 #ifdef CONFIG_CMD_NAND
278 #define CONFIG_NAND_ATMEL
279 #define CONFIG_SYS_MAX_NAND_DEVICE		1
280 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
281 #define CONFIG_SYS_NAND_DBW_8			1
282 /* our ALE is AD21 */
283 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
284 /* our CLE is AD22 */
285 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
286 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
287 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
288 #endif
289 
290 /* Ethernet */
291 #define CONFIG_MACB			1
292 #define CONFIG_RMII			1
293 #define CONFIG_NET_RETRY_COUNT		20
294 #define CONFIG_RESET_PHY_R		1
295 
296 /* USB */
297 #define CONFIG_USB_ATMEL
298 #define CONFIG_USB_OHCI_NEW		1
299 #define CONFIG_DOS_PARTITION		1
300 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
301 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
302 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
303 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
304 #define CONFIG_USB_STORAGE		1
305 #define CONFIG_CMD_FAT			1
306 
307 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
308 
309 #define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
310 #define CONFIG_SYS_MEMTEST_END			0x23e00000
311 
312 #ifdef CONFIG_SYS_USE_DATAFLASH
313 
314 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
315 #define CONFIG_ENV_IS_IN_DATAFLASH	1
316 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
317 #define CONFIG_ENV_OFFSET		0x4200
318 #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
319 #define CONFIG_ENV_SIZE		0x4200
320 #define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
321 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
322 				"root=/dev/mtdblock0 " \
323 				"mtdparts=atmel_nand:-(root) "\
324 				"rw rootfstype=jffs2"
325 
326 #elif CONFIG_SYS_USE_NANDFLASH
327 
328 /* bootstrap + u-boot + env + linux in nandflash */
329 #define CONFIG_ENV_IS_IN_NAND		1
330 #define CONFIG_ENV_OFFSET		0x60000
331 #define CONFIG_ENV_OFFSET_REDUND	0x80000
332 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
333 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
334 #define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
335 				"root=/dev/mtdblock5 " \
336 				"mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
337 				"rw rootfstype=jffs2"
338 
339 #endif
340 
341 #define CONFIG_SYS_PROMPT		"U-Boot> "
342 #define CONFIG_SYS_CBSIZE		256
343 #define CONFIG_SYS_MAXARGS		16
344 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
345 #define CONFIG_SYS_LONGHELP		1
346 #define CONFIG_CMDLINE_EDITING		1
347 #define CONFIG_AUTO_COMPLETE
348 #define CONFIG_SYS_HUSH_PARSER
349 
350 /*
351  * Size of malloc() pool
352  */
353 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
354 
355 #endif
356