1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9263EK board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * SoC must be defined first, before hardware.h is included. 16 * In this case SoC is defined in boards.cfg. 17 */ 18 #include <asm/hardware.h> 19 20 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 21 #define CONFIG_SYS_TEXT_BASE 0x21F00000 22 #else 23 #define CONFIG_SYS_TEXT_BASE 0x0000000 24 #endif 25 26 /* ARM asynchronous clock */ 27 #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ 28 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 29 30 #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ 31 32 #define CONFIG_ARCH_CPU_INIT 33 34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35 #define CONFIG_SETUP_MEMORY_TAGS 1 36 #define CONFIG_INITRD_TAG 1 37 38 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 39 #define CONFIG_SKIP_LOWLEVEL_INIT 40 #else 41 #define CONFIG_SYS_USE_NORFLASH 42 #endif 43 44 #define CONFIG_BOARD_EARLY_INIT_F 45 46 /* 47 * Hardware drivers 48 */ 49 #define CONFIG_ATMEL_LEGACY 50 #define CONFIG_AT91_GPIO 1 51 #define CONFIG_AT91_GPIO_PULLUP 1 52 53 /* serial console */ 54 #define CONFIG_ATMEL_USART 55 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 56 #define CONFIG_USART_ID ATMEL_ID_SYS 57 #define CONFIG_BAUDRATE 115200 58 59 /* LCD */ 60 #define LCD_BPP LCD_COLOR8 61 #define CONFIG_LCD_LOGO 1 62 #undef LCD_TEST_PATTERN 63 #define CONFIG_LCD_INFO 1 64 #define CONFIG_LCD_INFO_BELOW_LOGO 1 65 #define CONFIG_SYS_WHITE_ON_BLACK 1 66 #define CONFIG_ATMEL_LCD 1 67 #define CONFIG_ATMEL_LCD_BGR555 1 68 69 /* LED */ 70 #define CONFIG_AT91_LED 71 #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ 72 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ 73 #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ 74 75 76 /* 77 * BOOTP options 78 */ 79 #define CONFIG_BOOTP_BOOTFILESIZE 1 80 #define CONFIG_BOOTP_BOOTPATH 1 81 #define CONFIG_BOOTP_GATEWAY 1 82 #define CONFIG_BOOTP_HOSTNAME 1 83 84 /* 85 * Command line configuration. 86 */ 87 #define CONFIG_CMD_NAND 1 88 89 /* SDRAM */ 90 #define CONFIG_NR_DRAM_BANKS 1 91 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 92 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 93 94 #define CONFIG_SYS_INIT_SP_ADDR \ 95 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) 96 97 /* DataFlash */ 98 #define CONFIG_ATMEL_DATAFLASH_SPI 99 #define CONFIG_HAS_DATAFLASH 1 100 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 101 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 102 #define AT91_SPI_CLK 15000000 103 #define DATAFLASH_TCSS (0x1a << 16) 104 #define DATAFLASH_TCHS (0x1 << 24) 105 106 /* MMC */ 107 #ifdef CONFIG_CMD_MMC 108 #define CONFIG_GENERIC_MMC 109 #define CONFIG_GENERIC_ATMEL_MCI 110 #endif 111 112 /* NOR flash, if populated */ 113 #ifdef CONFIG_SYS_USE_NORFLASH 114 #define CONFIG_SYS_FLASH_CFI 1 115 #define CONFIG_FLASH_CFI_DRIVER 1 116 #define PHYS_FLASH_1 0x10000000 117 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 118 #define CONFIG_SYS_MAX_FLASH_SECT 256 119 #define CONFIG_SYS_MAX_FLASH_BANKS 1 120 121 #define CONFIG_SYS_MONITOR_SEC 1:0-3 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 123 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 124 #define CONFIG_ENV_IS_IN_FLASH 1 125 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) 126 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) 127 128 /* Address and size of Primary Environment Sector */ 129 #define CONFIG_ENV_SIZE 0x10000 130 131 #define CONFIG_EXTRA_ENV_SETTINGS \ 132 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 133 "update=" \ 134 "protect off ${monitor_base} +${filesize};" \ 135 "erase ${monitor_base} +${filesize};" \ 136 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ 137 "protect on ${monitor_base} +${filesize}\0" 138 139 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 140 #define MASTER_PLL_MUL 171 141 #define MASTER_PLL_DIV 14 142 #define MASTER_PLL_OUT 3 143 144 /* clocks */ 145 #define CONFIG_SYS_MOR_VAL \ 146 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 147 #define CONFIG_SYS_PLLAR_VAL \ 148 (AT91_PMC_PLLAR_29 | \ 149 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 150 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 151 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 152 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 153 154 /* PCK/2 = MCK Master Clock from PLLA */ 155 #define CONFIG_SYS_MCKR1_VAL \ 156 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 157 AT91_PMC_MCKR_MDIV_2) 158 159 /* PCK/2 = MCK Master Clock from PLLA */ 160 #define CONFIG_SYS_MCKR2_VAL \ 161 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 162 AT91_PMC_MCKR_MDIV_2) 163 164 /* define PDC[31:16] as DATA[31:16] */ 165 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 166 /* no pull-up for D[31:16] */ 167 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 168 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 169 #define CONFIG_SYS_MATRIX_EBICSA_VAL \ 170 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 171 AT91_MATRIX_CSA_EBI_CS1A) 172 173 /* SDRAM */ 174 /* SDRAMC_MR Mode register */ 175 #define CONFIG_SYS_SDRC_MR_VAL1 0 176 /* SDRAMC_TR - Refresh Timer register */ 177 #define CONFIG_SYS_SDRC_TR_VAL1 0x13C 178 /* SDRAMC_CR - Configuration register*/ 179 #define CONFIG_SYS_SDRC_CR_VAL \ 180 (AT91_SDRAMC_NC_9 | \ 181 AT91_SDRAMC_NR_13 | \ 182 AT91_SDRAMC_NB_4 | \ 183 AT91_SDRAMC_CAS_3 | \ 184 AT91_SDRAMC_DBW_32 | \ 185 (1 << 8) | /* Write Recovery Delay */ \ 186 (7 << 12) | /* Row Cycle Delay */ \ 187 (2 << 16) | /* Row Precharge Delay */ \ 188 (2 << 20) | /* Row to Column Delay */ \ 189 (5 << 24) | /* Active to Precharge Delay */ \ 190 (1 << 28)) /* Exit Self Refresh to Active Delay */ 191 192 /* Memory Device Register -> SDRAM */ 193 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 194 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 195 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 196 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 197 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 198 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 199 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 200 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 201 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 202 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 203 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 204 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 205 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 206 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 207 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 208 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 209 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 210 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 211 212 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 213 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 214 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 215 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 216 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 217 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 218 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 219 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 220 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 221 #define CONFIG_SYS_SMC0_MODE0_VAL \ 222 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 223 AT91_SMC_MODE_DBW_16 | \ 224 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 225 226 /* user reset enable */ 227 #define CONFIG_SYS_RSTC_RMR_VAL \ 228 (AT91_RSTC_KEY | \ 229 AT91_RSTC_MR_URSTEN | \ 230 AT91_RSTC_MR_ERSTL(15)) 231 232 /* Disable Watchdog */ 233 #define CONFIG_SYS_WDTC_WDMR_VAL \ 234 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 235 AT91_WDT_MR_WDV(0xfff) | \ 236 AT91_WDT_MR_WDDIS | \ 237 AT91_WDT_MR_WDD(0xfff)) 238 239 #endif 240 241 #else 242 #define CONFIG_SYS_NO_FLASH 1 243 #endif 244 245 /* NAND flash */ 246 #ifdef CONFIG_CMD_NAND 247 #define CONFIG_NAND_ATMEL 248 #define CONFIG_SYS_MAX_NAND_DEVICE 1 249 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 250 #define CONFIG_SYS_NAND_DBW_8 1 251 /* our ALE is AD21 */ 252 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 253 /* our CLE is AD22 */ 254 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 255 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 256 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 257 #endif 258 259 /* Ethernet */ 260 #define CONFIG_MACB 1 261 #define CONFIG_RMII 1 262 #define CONFIG_NET_RETRY_COUNT 20 263 #define CONFIG_RESET_PHY_R 1 264 #define CONFIG_AT91_WANTS_COMMON_PHY 265 266 /* USB */ 267 #define CONFIG_USB_ATMEL 268 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 269 #define CONFIG_USB_OHCI_NEW 1 270 #define CONFIG_DOS_PARTITION 1 271 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 272 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ 273 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 274 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 275 276 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 277 278 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 279 #define CONFIG_SYS_MEMTEST_END 0x23e00000 280 281 #ifdef CONFIG_SYS_USE_DATAFLASH 282 283 /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 284 #define CONFIG_ENV_IS_IN_DATAFLASH 1 285 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 286 #define CONFIG_ENV_OFFSET 0x4200 287 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 288 #define CONFIG_ENV_SIZE 0x4200 289 #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" 290 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 291 "root=/dev/mtdblock0 " \ 292 "mtdparts=atmel_nand:-(root) "\ 293 "rw rootfstype=jffs2" 294 295 #elif CONFIG_SYS_USE_NANDFLASH 296 297 /* bootstrap + u-boot + env + linux in nandflash */ 298 #define CONFIG_ENV_IS_IN_NAND 1 299 #define CONFIG_ENV_OFFSET 0xc0000 300 #define CONFIG_ENV_OFFSET_REDUND 0x100000 301 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 302 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" 303 #define CONFIG_BOOTARGS \ 304 "console=ttyS0,115200 earlyprintk " \ 305 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 306 "256k(env),256k(env_redundant),256k(spare)," \ 307 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 308 "root=/dev/mtdblock7 rw rootfstype=jffs2" 309 #endif 310 311 #define CONFIG_SYS_CBSIZE 256 312 #define CONFIG_SYS_MAXARGS 16 313 #define CONFIG_SYS_LONGHELP 1 314 #define CONFIG_CMDLINE_EDITING 1 315 #define CONFIG_AUTO_COMPLETE 316 317 /* 318 * Size of malloc() pool 319 */ 320 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 321 322 #endif 323