xref: /openbmc/u-boot/include/configs/at91sam9263ek.h (revision 0f44d33536a50ef65259c322fa2d4a058585caf9)
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * Configuation settings for the AT91SAM9263EK board.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /*
15  * SoC must be defined first, before hardware.h is included.
16  * In this case SoC is defined in boards.cfg.
17  */
18 #include <asm/hardware.h>
19 
20 /* ARM asynchronous clock */
21 #define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
22 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
23 
24 #define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
25 
26 #define CONFIG_ARCH_CPU_INIT
27 
28 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
29 #define CONFIG_SETUP_MEMORY_TAGS 1
30 #define CONFIG_INITRD_TAG	1
31 
32 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
33 #define CONFIG_SKIP_LOWLEVEL_INIT
34 #else
35 #define CONFIG_SYS_USE_NORFLASH
36 #endif
37 
38 /*
39  * Hardware drivers
40  */
41 #define CONFIG_ATMEL_LEGACY
42 
43 /* LCD */
44 #define LCD_BPP				LCD_COLOR8
45 #define CONFIG_LCD_LOGO			1
46 #undef LCD_TEST_PATTERN
47 #define CONFIG_LCD_INFO			1
48 #define CONFIG_LCD_INFO_BELOW_LOGO	1
49 #define CONFIG_ATMEL_LCD		1
50 #define CONFIG_ATMEL_LCD_BGR555		1
51 
52 /*
53  * BOOTP options
54  */
55 #define CONFIG_BOOTP_BOOTFILESIZE	1
56 #define CONFIG_BOOTP_BOOTPATH		1
57 #define CONFIG_BOOTP_GATEWAY		1
58 #define CONFIG_BOOTP_HOSTNAME		1
59 
60 /* SDRAM */
61 #define CONFIG_NR_DRAM_BANKS		1
62 #define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
63 #define CONFIG_SYS_SDRAM_SIZE		0x04000000
64 
65 #define CONFIG_SYS_INIT_SP_ADDR \
66 	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
67 
68 /* NOR flash, if populated */
69 #ifdef CONFIG_SYS_USE_NORFLASH
70 #define CONFIG_SYS_FLASH_CFI			1
71 #define CONFIG_FLASH_CFI_DRIVER			1
72 #define PHYS_FLASH_1				0x10000000
73 #define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
74 #define CONFIG_SYS_MAX_FLASH_SECT		256
75 #define CONFIG_SYS_MAX_FLASH_BANKS		1
76 
77 #define CONFIG_SYS_MONITOR_SEC	1:0-3
78 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
79 #define CONFIG_SYS_MONITOR_LEN	(256 << 10)
80 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
81 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
82 
83 /* Address and size of Primary Environment Sector */
84 #define CONFIG_ENV_SIZE		0x10000
85 
86 #define CONFIG_EXTRA_ENV_SETTINGS	\
87 	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
88 	"update=" \
89 		"protect off ${monitor_base} +${filesize};" \
90 		"erase ${monitor_base} +${filesize};" \
91 		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
92 		"protect on ${monitor_base} +${filesize}\0"
93 
94 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
95 #define MASTER_PLL_MUL		171
96 #define MASTER_PLL_DIV		14
97 #define MASTER_PLL_OUT		3
98 
99 /* clocks */
100 #define CONFIG_SYS_MOR_VAL						\
101 		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
102 #define CONFIG_SYS_PLLAR_VAL					\
103 	(AT91_PMC_PLLAR_29 |					\
104 	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
105 	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
106 	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
107 	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
108 
109 /* PCK/2 = MCK Master Clock from PLLA */
110 #define	CONFIG_SYS_MCKR1_VAL		\
111 	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
112 	 AT91_PMC_MCKR_MDIV_2)
113 
114 /* PCK/2 = MCK Master Clock from PLLA */
115 #define	CONFIG_SYS_MCKR2_VAL		\
116 	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
117 	AT91_PMC_MCKR_MDIV_2)
118 
119 /* define PDC[31:16] as DATA[31:16] */
120 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
121 /* no pull-up for D[31:16] */
122 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
123 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
124 #define CONFIG_SYS_MATRIX_EBICSA_VAL					\
125 	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
126 	 AT91_MATRIX_CSA_EBI_CS1A)
127 
128 /* SDRAM */
129 /* SDRAMC_MR Mode register */
130 #define CONFIG_SYS_SDRC_MR_VAL1		0
131 /* SDRAMC_TR - Refresh Timer register */
132 #define CONFIG_SYS_SDRC_TR_VAL1		0x13C
133 /* SDRAMC_CR - Configuration register*/
134 #define CONFIG_SYS_SDRC_CR_VAL							\
135 		(AT91_SDRAMC_NC_9 |						\
136 		 AT91_SDRAMC_NR_13 |						\
137 		 AT91_SDRAMC_NB_4 |						\
138 		 AT91_SDRAMC_CAS_3 |						\
139 		 AT91_SDRAMC_DBW_32 |						\
140 		 (1 <<  8) |		/* Write Recovery Delay */		\
141 		 (7 << 12) |		/* Row Cycle Delay */			\
142 		 (2 << 16) |		/* Row Precharge Delay */		\
143 		 (2 << 20) |		/* Row to Column Delay */		\
144 		 (5 << 24) |		/* Active to Precharge Delay */		\
145 		 (1 << 28))		/* Exit Self Refresh to Active Delay */
146 
147 /* Memory Device Register -> SDRAM */
148 #define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
149 #define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
150 #define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
151 #define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
152 #define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
153 #define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
154 #define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
155 #define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
156 #define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
157 #define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
158 #define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
159 #define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
160 #define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
161 #define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
162 #define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
163 #define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
164 #define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
165 #define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
166 
167 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
168 #define CONFIG_SYS_SMC0_SETUP0_VAL				\
169 	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
170 	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
171 #define CONFIG_SYS_SMC0_PULSE0_VAL				\
172 	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
173 	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
174 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
175 	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
176 #define CONFIG_SYS_SMC0_MODE0_VAL				\
177 	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
178 	 AT91_SMC_MODE_DBW_16 |					\
179 	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
180 
181 /* user reset enable */
182 #define CONFIG_SYS_RSTC_RMR_VAL			\
183 		(AT91_RSTC_KEY |		\
184 		AT91_RSTC_MR_URSTEN |		\
185 		AT91_RSTC_MR_ERSTL(15))
186 
187 /* Disable Watchdog */
188 #define CONFIG_SYS_WDTC_WDMR_VAL				\
189 		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
190 		 AT91_WDT_MR_WDV(0xfff) |			\
191 		 AT91_WDT_MR_WDDIS |				\
192 		 AT91_WDT_MR_WDD(0xfff))
193 
194 #endif
195 #endif
196 
197 /* NAND flash */
198 #ifdef CONFIG_CMD_NAND
199 #define CONFIG_NAND_ATMEL
200 #define CONFIG_SYS_MAX_NAND_DEVICE		1
201 #define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
202 #define CONFIG_SYS_NAND_DBW_8			1
203 /* our ALE is AD21 */
204 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
205 /* our CLE is AD22 */
206 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
207 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
208 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
209 #endif
210 
211 /* Ethernet */
212 #define CONFIG_RESET_PHY_R		1
213 #define CONFIG_AT91_WANTS_COMMON_PHY
214 
215 /* USB */
216 #define CONFIG_USB_ATMEL
217 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
218 #define CONFIG_USB_OHCI_NEW		1
219 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
220 #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
221 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
222 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
223 
224 #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
225 
226 #define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
227 #define CONFIG_SYS_MEMTEST_END			0x23e00000
228 
229 #ifdef CONFIG_SYS_USE_DATAFLASH
230 
231 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
232 #define CONFIG_ENV_OFFSET	0x4200
233 #define CONFIG_ENV_SIZE		0x4200
234 #define CONFIG_ENV_SECT_SIZE	0x210
235 #define CONFIG_ENV_SPI_MAX_HZ	15000000
236 #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
237 				"sf read 0x22000000 0x84000 0x294000; " \
238 				"bootm 0x22000000"
239 
240 #elif CONFIG_SYS_USE_NANDFLASH
241 
242 /* bootstrap + u-boot + env + linux in nandflash */
243 #define CONFIG_ENV_OFFSET		0x120000
244 #define CONFIG_ENV_OFFSET_REDUND	0x100000
245 #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
246 #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
247 #endif
248 
249 #define CONFIG_SYS_LONGHELP		1
250 #define CONFIG_CMDLINE_EDITING		1
251 #define CONFIG_AUTO_COMPLETE
252 
253 /*
254  * Size of malloc() pool
255  */
256 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
257 
258 #endif
259