1 /*
2  * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
3  *
4  * based on previous work by
5  *
6  * Ulf Samuelsson <ulf@atmel.com>
7  * Rick Bronson <rick@efn.org>
8  *
9  * Configuration settings for the AT91RM9200EK board.
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #ifndef __AT91RM9200EK_CONFIG_H__
15 #define __AT91RM9200EK_CONFIG_H__
16 
17 #include <linux/sizes.h>
18 
19 /*
20  * set some initial configurations depending on configure target
21  *
22  * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
23  * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
24  *                            initialisation was done by some preloader
25  */
26 #ifdef CONFIG_RAMBOOT
27 #define CONFIG_SKIP_LOWLEVEL_INIT
28 #define CONFIG_SYS_TEXT_BASE 0x20100000
29 #else
30 #define CONFIG_SYS_TEXT_BASE 0x10000000
31 #endif
32 
33 /*
34  * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
35  * AT91C_MAIN_CLOCK is the frequency of PLLA output
36  * AT91C_MASTER_CLOCK is the peripherial clock
37  * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
38  *  set in arch/arm/cpu/arm920t/at91/timer.c)
39  * CONFIG_SYS_HZ is the tick rate for timer tc0
40  */
41 #define AT91C_XTAL_CLOCK		18432000
42 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
43 #define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
44 #define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
45 #define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
46 
47 /* CPU configuration */
48 #define CONFIG_AT91RM9200
49 #define CONFIG_AT91RM9200EK
50 #define CONFIG_CPUAT91
51 #define USE_920T_MMU
52 
53 #include <asm/hardware.h>	/* needed for port definitions */
54 
55 #define CONFIG_CMDLINE_TAG
56 #define CONFIG_SETUP_MEMORY_TAGS
57 #define CONFIG_INITRD_TAG
58 
59 #define CONFIG_BOARD_EARLY_INIT_F
60 
61 #define CONFIG_CMD_BOOTZ
62 #define CONFIG_OF_LIBFDT
63 
64 
65 /*
66  * Memory Configuration
67  */
68 #define CONFIG_NR_DRAM_BANKS		1
69 #define CONFIG_SYS_SDRAM_BASE		0x20000000
70 #define CONFIG_SYS_SDRAM_SIZE		SZ_32M
71 
72 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
73 #define CONFIG_SYS_MEMTEST_END		\
74 		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
75 
76 /*
77  * LowLevel Init
78  */
79 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
80 #define CONFIG_SYS_USE_MAIN_OSCILLATOR
81 /* flash */
82 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
83 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
84 
85 /* clocks */
86 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
87 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
88 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
89 #define CONFIG_SYS_MCKR_VAL	0x00000202
90 
91 /* sdram */
92 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
93 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
94 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
95 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
96 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
97 #define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
98 #define CONFIG_SYS_SDRAM1	(CONFIG_SYS_SDRAM_BASE+0x80)
99 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
100 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
101 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
102 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
103 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
104 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
105 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
106 
107 /*
108  * Hardware drivers
109  */
110 /*
111  * Choose a USART for serial console
112  * CONFIG_DBGU is DBGU unit on J10
113  * CONFIG_USART1 is USART1 on J14
114  */
115 #define CONFIG_ATMEL_USART
116 #define CONFIG_USART_BASE	ATMEL_BASE_DBGU
117 #define CONFIG_USART_ID		0/* ignored in arm */
118 
119 #define CONFIG_BAUDRATE			115200
120 
121 /*
122  * Command line configuration.
123  */
124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_FAT
126 #define CONFIG_CMD_MII
127 #define CONFIG_CMD_PING
128 #define CONFIG_CMD_USB
129 
130 /*
131  * Network Driver Setting
132  */
133 #define CONFIG_DRIVER_AT91EMAC
134 #define CONFIG_SYS_RX_ETH_BUFFER	16
135 #define CONFIG_RMII
136 #define CONFIG_MII
137 
138 /*
139  * NOR Flash
140  */
141 #define CONFIG_FLASH_CFI_DRIVER
142 #define CONFIG_SYS_FLASH_CFI
143 #define CONFIG_SYS_FLASH_BASE		0x10000000
144 #define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
145 #define PHYS_FLASH_SIZE			SZ_8M
146 #define CONFIG_SYS_MAX_FLASH_BANKS	1
147 #define CONFIG_SYS_MAX_FLASH_SECT	256
148 #define CONFIG_SYS_FLASH_PROTECTION
149 
150 /*
151  * USB Config
152  */
153 #define CONFIG_USB_ATMEL			1
154 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
155 #define CONFIG_USB_OHCI_NEW			1
156 #define CONFIG_USB_KEYBOARD			1
157 #define CONFIG_USB_STORAGE			1
158 #define CONFIG_DOS_PARTITION			1
159 
160 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
161 #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_USB_HOST_BASE
162 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
163 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
164 
165 /*
166  * Environment Settings
167  */
168 #define CONFIG_ENV_IS_IN_FLASH
169 
170 /*
171  * after u-boot.bin
172  */
173 #define CONFIG_ENV_ADDR			\
174 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
175 #define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
176 /* The following #defines are needed to get flash environment right */
177 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
178 #define CONFIG_SYS_MONITOR_LEN		SZ_256K
179 
180 /*
181  * Boot option
182  */
183 #define CONFIG_BOOTDELAY		3
184 
185 /* default load address */
186 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
187 #define CONFIG_ENV_OVERWRITE
188 
189 /*
190  * Shell Settings
191  */
192 #define CONFIG_CMDLINE_EDITING
193 #define CONFIG_SYS_LONGHELP
194 #define CONFIG_AUTO_COMPLETE
195 #define CONFIG_SYS_HUSH_PARSER
196 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
197 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
198 /* Print Buffer Size */
199 #define CONFIG_SYS_PBSIZE		\
200 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
201 
202 /*
203  * Size of malloc() pool
204  */
205 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
206 					     SZ_4K)
207 
208 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
209 					- GENERATED_GBL_DATA_SIZE)
210 
211 #endif /* __AT91RM9200EK_CONFIG_H__ */
212